JPS56130900A - Error corrector - Google Patents

Error corrector

Info

Publication number
JPS56130900A
JPS56130900A JP3386480A JP3386480A JPS56130900A JP S56130900 A JPS56130900 A JP S56130900A JP 3386480 A JP3386480 A JP 3386480A JP 3386480 A JP3386480 A JP 3386480A JP S56130900 A JPS56130900 A JP S56130900A
Authority
JP
Japan
Prior art keywords
circuit
error
control
correction
microinstruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3386480A
Other languages
Japanese (ja)
Inventor
Masahiro Yamashita
Hidenori Sankai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3386480A priority Critical patent/JPS56130900A/en
Publication of JPS56130900A publication Critical patent/JPS56130900A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To make error check and correction before the execution of microinstruction, by sequentially addressing the control memory device at the error detecting condition to be satisfied such as CPU waiting time and making the parity check and write-in correction of data. CONSTITUTION:When CPU is in waiting state and the error detecting condition 6 is established, the AND gate is open, and data are read out from CS3 with the address sequentially formed with the address forming circuit 7 consisting of the counter, control circuit and final address deciding comparison circuit and the like and the readout signal from the control stroage device (CS) control device 6, and parity check is made at the error detection circuit 9. Further, when the parity error detection signal is generated from the circuit 9, the rewrite-in and correction for the data is made. Thus, before the microinstruction is executed through the control of CS3 via the circuit 2 and the like, error check and error correction are made, allowing to prevent the production of system stop during the execution of microinstruction.
JP3386480A 1980-03-19 1980-03-19 Error corrector Pending JPS56130900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3386480A JPS56130900A (en) 1980-03-19 1980-03-19 Error corrector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3386480A JPS56130900A (en) 1980-03-19 1980-03-19 Error corrector

Publications (1)

Publication Number Publication Date
JPS56130900A true JPS56130900A (en) 1981-10-14

Family

ID=12398360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3386480A Pending JPS56130900A (en) 1980-03-19 1980-03-19 Error corrector

Country Status (1)

Country Link
JP (1) JPS56130900A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04260147A (en) * 1991-02-15 1992-09-16 Nec Corp Diagnostic system for local memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04260147A (en) * 1991-02-15 1992-09-16 Nec Corp Diagnostic system for local memory

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