JPS5757327A - Clock synchronous system for douplexed information processor - Google Patents

Clock synchronous system for douplexed information processor

Info

Publication number
JPS5757327A
JPS5757327A JP13202380A JP13202380A JPS5757327A JP S5757327 A JPS5757327 A JP S5757327A JP 13202380 A JP13202380 A JP 13202380A JP 13202380 A JP13202380 A JP 13202380A JP S5757327 A JPS5757327 A JP S5757327A
Authority
JP
Japan
Prior art keywords
output
clock
phase
oscillator
microrunaway
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13202380A
Other languages
Japanese (ja)
Inventor
Toshinori Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13202380A priority Critical patent/JPS5757327A/en
Publication of JPS5757327A publication Critical patent/JPS5757327A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Landscapes

  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To prevent the microrunaway due to the switching of clock sources, by detecting and reducing the difference of phase between the clock outputs of the duplexed information processors that oscillate independently of each other and securing the synchronism for the phases of the clock oscillation outputs. CONSTITUTION:A shift of phase is caused between an output 1 of an oscillator of own system and an output 2 of an oscillator of another system when the power source is applied, and the pulse emerges at the output of an exclusive OR5. This pulse, the output 1 and a control output 4 to the system that causes a shift of phase are supplied to an AND gate 5. An FF11 monitors the break of clock of other system, and its output is 0 if no clock is broken for other system. The output of the gate 5 is put into the clock input of a counter 6 to be counted up by one, and the output of the counter is decoded 7 to select an old number of a delay line 8. The delayed output of an oscillator of own system emerges at a terminal 10, and this action is continued until coincidence of phase is obtained the oscillators of both systems. As a result, the continuance of cock due to the clock switching can be held to prevent a microrunaway.
JP13202380A 1980-09-22 1980-09-22 Clock synchronous system for douplexed information processor Pending JPS5757327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13202380A JPS5757327A (en) 1980-09-22 1980-09-22 Clock synchronous system for douplexed information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13202380A JPS5757327A (en) 1980-09-22 1980-09-22 Clock synchronous system for douplexed information processor

Publications (1)

Publication Number Publication Date
JPS5757327A true JPS5757327A (en) 1982-04-06

Family

ID=15071699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13202380A Pending JPS5757327A (en) 1980-09-22 1980-09-22 Clock synchronous system for douplexed information processor

Country Status (1)

Country Link
JP (1) JPS5757327A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0659769A (en) * 1992-06-26 1994-03-04 Internatl Business Mach Corp <Ibm> Clock generating circuit of digital computer and method therefor
US6680989B1 (en) 1998-10-30 2004-01-20 Fujitsu Limited Method and apparatus for clock switching

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0659769A (en) * 1992-06-26 1994-03-04 Internatl Business Mach Corp <Ibm> Clock generating circuit of digital computer and method therefor
US6680989B1 (en) 1998-10-30 2004-01-20 Fujitsu Limited Method and apparatus for clock switching

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