JPS5750387A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5750387A
JPS5750387A JP55125471A JP12547180A JPS5750387A JP S5750387 A JPS5750387 A JP S5750387A JP 55125471 A JP55125471 A JP 55125471A JP 12547180 A JP12547180 A JP 12547180A JP S5750387 A JPS5750387 A JP S5750387A
Authority
JP
Japan
Prior art keywords
circuits
digit line
digit
constitution
sense amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55125471A
Other languages
Japanese (ja)
Other versions
JPS636952B2 (en
Inventor
Yasaburo Inagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55125471A priority Critical patent/JPS5750387A/en
Publication of JPS5750387A publication Critical patent/JPS5750387A/en
Publication of JPS636952B2 publication Critical patent/JPS636952B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To effectively reduce the CR time constnat of a digit line, by connecting various circuits to the center part of a pair of digit lines. CONSTITUTION:Precharging circuits 11 and 12, a sense amplifier 21, Y and X decoder switches 31 and 32, loading circuits 41 and 42, etc. are arranged at the center part between a real digit line 1 and an auxiliary digit line 2. With such arrangement of circuits, both the capacity value and the resistance value are reduced down to 1/2 in comparison with a constitution in which various circuits are arranged by one channel respectively at the end of the sense amplifier circuit side of both digit lines. Accordingly, the CR time constant of the digit line is effectively reduced. As a result, a high-speed operation is possible for a memory device.
JP55125471A 1980-09-10 1980-09-10 Memory device Granted JPS5750387A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55125471A JPS5750387A (en) 1980-09-10 1980-09-10 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55125471A JPS5750387A (en) 1980-09-10 1980-09-10 Memory device

Publications (2)

Publication Number Publication Date
JPS5750387A true JPS5750387A (en) 1982-03-24
JPS636952B2 JPS636952B2 (en) 1988-02-13

Family

ID=14910902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55125471A Granted JPS5750387A (en) 1980-09-10 1980-09-10 Memory device

Country Status (1)

Country Link
JP (1) JPS5750387A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0139833A2 (en) * 1983-08-31 1985-05-08 Kabushiki Kaisha Toshiba CMOS transmission circuit
DE112016007077T5 (en) 2016-08-22 2019-04-04 Mitsubishi Electric Corporation COMMUNICATION DEVICE AND BANDWIDTH CONTROL METHOD

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5264236A (en) * 1975-11-21 1977-05-27 Toshiba Corp Dynamic memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5264236A (en) * 1975-11-21 1977-05-27 Toshiba Corp Dynamic memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0139833A2 (en) * 1983-08-31 1985-05-08 Kabushiki Kaisha Toshiba CMOS transmission circuit
DE112016007077T5 (en) 2016-08-22 2019-04-04 Mitsubishi Electric Corporation COMMUNICATION DEVICE AND BANDWIDTH CONTROL METHOD

Also Published As

Publication number Publication date
JPS636952B2 (en) 1988-02-13

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