JPS5743241A - Operating system with right shift - Google Patents

Operating system with right shift

Info

Publication number
JPS5743241A
JPS5743241A JP11926780A JP11926780A JPS5743241A JP S5743241 A JPS5743241 A JP S5743241A JP 11926780 A JP11926780 A JP 11926780A JP 11926780 A JP11926780 A JP 11926780A JP S5743241 A JPS5743241 A JP S5743241A
Authority
JP
Japan
Prior art keywords
check
operand
adder
result
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11926780A
Other languages
Japanese (ja)
Inventor
Kazutoshi Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11926780A priority Critical patent/JPS5743241A/en
Publication of JPS5743241A publication Critical patent/JPS5743241A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To obtain correct result of operation in high speed, by neglecting the data shifted out below the decimal point of the specified operand after right shift while controlling the carry input of adder, and making operation processing with another operand. CONSTITUTION:A data check section 25 makes zero check of lower priority data for shift digit number N's share of the specified operand picked up via a multiplexer 19 and an adder 21 sequentially from the lower priority digit of the prescribed operand register 17, when the prescribed operand is right shifted. Further, the check stores the result of zero check. An adder control section 26 is operated with the control of a +1 program control section 14, and as the result of the check of a code check section 14, further depending on the result of the check of the check section 25, the designation of addition/subtraction mode to the adder 21 and carry control are made to execute the operation processing with another operand.
JP11926780A 1980-08-29 1980-08-29 Operating system with right shift Pending JPS5743241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11926780A JPS5743241A (en) 1980-08-29 1980-08-29 Operating system with right shift

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11926780A JPS5743241A (en) 1980-08-29 1980-08-29 Operating system with right shift

Publications (1)

Publication Number Publication Date
JPS5743241A true JPS5743241A (en) 1982-03-11

Family

ID=14757107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11926780A Pending JPS5743241A (en) 1980-08-29 1980-08-29 Operating system with right shift

Country Status (1)

Country Link
JP (1) JPS5743241A (en)

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