JPS57153363A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS57153363A JPS57153363A JP3908281A JP3908281A JPS57153363A JP S57153363 A JPS57153363 A JP S57153363A JP 3908281 A JP3908281 A JP 3908281A JP 3908281 A JP3908281 A JP 3908281A JP S57153363 A JPS57153363 A JP S57153363A
- Authority
- JP
- Japan
- Prior art keywords
- data
- signal line
- transferred
- control
- cpu9
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Calculators And Similar Devices (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To increase the processing efficiency, by making processing for other data, independently of the execution of the other data. CONSTITUTION:When a numerical data inputted from the operation of a ten key input section 2 is used as a numberical data for operation, numerical data inputted via a signal line L4 from a ten key input section 2 are transferred to a CPU9 via a signal line L5 by the control of a control circuit 7. After the execution of operation, if the operator uses the result of operation processed at the CPU9 as the data on a program under the control of a CPU8, a latch circuit is operated by applying a switch 6, and the result of operation transferred via a signal line L7 is transferred to a main storage device 10 of the CPU8 through signal lines L9 and L10.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3908281A JPS57153363A (en) | 1981-03-17 | 1981-03-17 | Data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3908281A JPS57153363A (en) | 1981-03-17 | 1981-03-17 | Data processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57153363A true JPS57153363A (en) | 1982-09-21 |
Family
ID=12543165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3908281A Pending JPS57153363A (en) | 1981-03-17 | 1981-03-17 | Data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57153363A (en) |
-
1981
- 1981-03-17 JP JP3908281A patent/JPS57153363A/en active Pending
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