JPS5739458A - Operation history memory device - Google Patents
Operation history memory deviceInfo
- Publication number
- JPS5739458A JPS5739458A JP55112969A JP11296980A JPS5739458A JP S5739458 A JPS5739458 A JP S5739458A JP 55112969 A JP55112969 A JP 55112969A JP 11296980 A JP11296980 A JP 11296980A JP S5739458 A JPS5739458 A JP S5739458A
- Authority
- JP
- Japan
- Prior art keywords
- register
- address
- read
- contents
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To read out effective words in order from the oldest in the words written in former times, by comparing contents of a write register with those of a start register, and completing read-out at the time of coincidence, in case when a start address register is read out as increment. CONSTITUTION:In accordance with a write instruction, contents of a write address register 16 become A+1 from A by counter 18, and at the same time contents of a write data buffer register 13 in that case are stored in the address A of a memory circuit. Then, increment and write are executed in order until an operation command is generated. Subsequently, in accordance with a read-out instruction, a start address register 17 passes through an address register 15, is provided to a memory circuit 12, and contents of B-1 address are read out to a read-out buffer register 14. Then, the address B is read out in the same way, the start address register 17 becomes B+1, and when it coincides with the register 16, a signal showing that the address B is final is outputted from a comparing circuit 20, and a read-out end signal and the contents of the address B are outputted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55112969A JPS5739458A (en) | 1980-08-19 | 1980-08-19 | Operation history memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55112969A JPS5739458A (en) | 1980-08-19 | 1980-08-19 | Operation history memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5739458A true JPS5739458A (en) | 1982-03-04 |
Family
ID=14600076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55112969A Pending JPS5739458A (en) | 1980-08-19 | 1980-08-19 | Operation history memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5739458A (en) |
-
1980
- 1980-08-19 JP JP55112969A patent/JPS5739458A/en active Pending
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