JPS5739435A - Reset system of microprocessor - Google Patents
Reset system of microprocessorInfo
- Publication number
- JPS5739435A JPS5739435A JP55114550A JP11455080A JPS5739435A JP S5739435 A JPS5739435 A JP S5739435A JP 55114550 A JP55114550 A JP 55114550A JP 11455080 A JP11455080 A JP 11455080A JP S5739435 A JPS5739435 A JP S5739435A
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- outgoing
- firmware
- level
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To release a microprocessor automatically and also in a short time even in case when runaway of firmware has occured, by forcibly resetting the microprocessor at every constant time. CONSTITUTION:A multivibrator MV executes oscillation by about 50Hz, it is counted by a counter CONT of the next stage, and when about 3 minutes have elapsed, a signal of an H level is provided to a reset terminal RES of a microprocessor MPU, by which firmware is initialized forcibly. At the same time, the whole output port of the microprocessor MPU becomes an L level. On the other hand, in order not to interrupt normal outgoing (data) operation, call outgoing operation and incoming operation, in the outgoing (data) operation and the incoming operation, when each operation is started, its operation is detected and the counter CONT is cleared by utilizing the fact that it does not take 3 minutes until its whole sequence ends.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55114550A JPS5739435A (en) | 1980-08-20 | 1980-08-20 | Reset system of microprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55114550A JPS5739435A (en) | 1980-08-20 | 1980-08-20 | Reset system of microprocessor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5739435A true JPS5739435A (en) | 1982-03-04 |
Family
ID=14640587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55114550A Pending JPS5739435A (en) | 1980-08-20 | 1980-08-20 | Reset system of microprocessor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5739435A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS621046U (en) * | 1985-06-19 | 1987-01-07 |
-
1980
- 1980-08-20 JP JP55114550A patent/JPS5739435A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS621046U (en) * | 1985-06-19 | 1987-01-07 | ||
JPH0315959Y2 (en) * | 1985-06-19 | 1991-04-05 |
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