JPS5673384A - Time counting device - Google Patents

Time counting device

Info

Publication number
JPS5673384A
JPS5673384A JP15100679A JP15100679A JPS5673384A JP S5673384 A JPS5673384 A JP S5673384A JP 15100679 A JP15100679 A JP 15100679A JP 15100679 A JP15100679 A JP 15100679A JP S5673384 A JPS5673384 A JP S5673384A
Authority
JP
Japan
Prior art keywords
timer
time
counter
subtraction
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15100679A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Idokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15100679A priority Critical patent/JPS5673384A/en
Publication of JPS5673384A publication Critical patent/JPS5673384A/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

PURPOSE: To enable to stop an output of a timer signal by means of a simple memory constitution by a method wherein a timer signal is inverted after a time period which is a set time period multiplied by an integer has elapsed by using an integral memory.
CONSTITUTION: When a timer time set in a memory 3 of a timer time setting unit 2 and the present time by a counter 1 coincide with each other, a FF8 is set through a coincidence signal from a coincidence discrimination circuit 6, and a high level set output becomes a timer signal. On the other hand, a counter 9 starts a subtraction count to a preset value by means of the coincidence output of the circuit 6 and every time a subtraction ends, a subtraction end signal is applied to a counter 10 wherein a integral value is set by means of a memory 51 and at the same time, the counter 9 repeats a subtraction from the preset value. And when the content of the counter 10 performing subtraction becomes zero in answer to the subtraction end signal, the FF8 to which an end signal is applied from the counter 10 is reset, thus, the timer signal is inverted. With this, after a time period of a reset time multiplied by a set integral numeric has elapsed, a timer can be stopped by means of a simple constitution in which a plurality of timer time stored memories are unnecessitated.
COPYRIGHT: (C)1981,JPO&Japio
JP15100679A 1979-11-21 1979-11-21 Time counting device Pending JPS5673384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15100679A JPS5673384A (en) 1979-11-21 1979-11-21 Time counting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15100679A JPS5673384A (en) 1979-11-21 1979-11-21 Time counting device

Publications (1)

Publication Number Publication Date
JPS5673384A true JPS5673384A (en) 1981-06-18

Family

ID=15509222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15100679A Pending JPS5673384A (en) 1979-11-21 1979-11-21 Time counting device

Country Status (1)

Country Link
JP (1) JPS5673384A (en)

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