JPS5737948A - Am stereo receiver - Google Patents
Am stereo receiverInfo
- Publication number
- JPS5737948A JPS5737948A JP11171880A JP11171880A JPS5737948A JP S5737948 A JPS5737948 A JP S5737948A JP 11171880 A JP11171880 A JP 11171880A JP 11171880 A JP11171880 A JP 11171880A JP S5737948 A JPS5737948 A JP S5737948A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- sum
- level
- difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/86—Arrangements characterised by the broadcast information itself
- H04H20/88—Stereophonic broadcast systems
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
PURPOSE:To improve the stereo separation, by providing a frequency characteristic compensation circuit with a difference signal transmission circuit of an AM stereo reception and coinciding relative audible frequency characteristics of sum and difference signals. CONSTITUTION:A sum signal component in amplitude modulation is formed with an AM detector 5 and the signal is inputted to a matrix circuit 13 and an AGC filter 6. The difference signal component in phase modulation is detected at a PM detector 8 via a limiter amplifier 7 and the signal is inputted to a frequency characteristic correction circuit 14 and an LPF12. In the circuit 14, the level of low frequency part is decreased so as to coincide the audible frequency characteristics of the difference signal with that of the sum signal, and the level of high frequency component is increased to input the difference signal to a variable gain circuit 9. The circuit 9 is controlled with an AGC voltage from the filter 6 and the level of the difference signal is followed to the level of the sum signal and inputted to the circuit 13 via a muting circuit 11 for stereo/monaural switching. The sum and difference signals are synthesized at the circuit 13 and outputted with separation into left and right signals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11171880A JPS5737948A (en) | 1980-08-15 | 1980-08-15 | Am stereo receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11171880A JPS5737948A (en) | 1980-08-15 | 1980-08-15 | Am stereo receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5737948A true JPS5737948A (en) | 1982-03-02 |
JPS6234305B2 JPS6234305B2 (en) | 1987-07-25 |
Family
ID=14568398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11171880A Granted JPS5737948A (en) | 1980-08-15 | 1980-08-15 | Am stereo receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5737948A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100668951B1 (en) | 2005-11-17 | 2007-01-12 | 주식회사 포스코 | Auto looping apparatus for wire |
-
1980
- 1980-08-15 JP JP11171880A patent/JPS5737948A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100668951B1 (en) | 2005-11-17 | 2007-01-12 | 주식회사 포스코 | Auto looping apparatus for wire |
Also Published As
Publication number | Publication date |
---|---|
JPS6234305B2 (en) | 1987-07-25 |
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