JPS573429A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To accomplish an inverter which receives an external input signal of a TTL level, the output of which increases to a power supply level only with one activated clock and in which high speed is possible, by connecting 12 sets of FETs with clocks and power supplies by a special method. CONSTITUTION:Twelve sets of insulation gate type field effect transistors T1-T12, a clock phi, and spare charging means 1, 2, and power supply VDD are connected as shown in Figure, and an input logical signal ADD, and reference level REF are located at nodes N5 and N6, respectively. With the activation of the clock O, a true logical output A' in phase with the input logical signal ADD is produced at a node N10, an auxiliary logical output in opposite phase is produced at a node N9. For example, when the input signal ADD is at high level, a reset clock P is at low level and the activated clock O is at high level, then nodes N1, N2 are at ground level and N3, N4 are at high level through the difference of current ability of the T3 and T4. Further, the level of the nodes N1, N3 thus determined drives a main amplifier consisting of the T7-T12.