JPS5690627A - Semiconductor circuit - Google Patents
Semiconductor circuitInfo
- Publication number
- JPS5690627A JPS5690627A JP16692479A JP16692479A JPS5690627A JP S5690627 A JPS5690627 A JP S5690627A JP 16692479 A JP16692479 A JP 16692479A JP 16692479 A JP16692479 A JP 16692479A JP S5690627 A JPS5690627 A JP S5690627A
- Authority
- JP
- Japan
- Prior art keywords
- nodes
- potential
- node
- potential difference
- fetq3
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
Landscapes
- Static Random-Access Memory (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To obtain an output at a high speed by detecting input signals with high sensitivity, by automatically driving a control circuit according to the potential difference between input signals. CONSTITUTION:Nodes N4 and N5 are previously charged to high potentials and at a proper stage, clock phi2 is held at a high potential. In this state, FETs Q1, Q2 and Q3 are all on and the potential of node N2 is determined by the beta ratio among FETs Q1, Q2 and Q3. Next, when nodes N4 and N5 have a potential difference by the 1st and 2nd input signals S1 and S2, FETQ3 decreases in conductivity and the potentials of nodes N2 and N1 rise. When the potential difference between nodes N4 and N5 exceeds the sensitivity of a control circuit, the voltage of node N1 turns on FETQ8 to drive the control circuit, increasing the potential difference between nodes N4 and N5. Consequently, the conductivity of FETQ3 further decreases and through regenerative feedback, node N4 is held at a low potential to the end to turn off FETQ3, thereby holding node N2 (output terminal) at a high potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16692479A JPS5690627A (en) | 1979-12-24 | 1979-12-24 | Semiconductor circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16692479A JPS5690627A (en) | 1979-12-24 | 1979-12-24 | Semiconductor circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5690627A true JPS5690627A (en) | 1981-07-22 |
JPS622729B2 JPS622729B2 (en) | 1987-01-21 |
Family
ID=15840174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16692479A Granted JPS5690627A (en) | 1979-12-24 | 1979-12-24 | Semiconductor circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5690627A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60114029A (en) * | 1983-11-21 | 1985-06-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Differential logic circuit |
JPH0469896A (en) * | 1990-07-10 | 1992-03-05 | Sharp Corp | Sense amplifying circuit |
-
1979
- 1979-12-24 JP JP16692479A patent/JPS5690627A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60114029A (en) * | 1983-11-21 | 1985-06-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Differential logic circuit |
JPH0469896A (en) * | 1990-07-10 | 1992-03-05 | Sharp Corp | Sense amplifying circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS622729B2 (en) | 1987-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6451822A (en) | Buffer circuit and integrated circuit using the same | |
JPS5625290A (en) | Semiconductor circuit | |
JPS57206113A (en) | Amplifier for limiter | |
JPS56168168A (en) | Window comparator circuit | |
GB1407980A (en) | Shift register stage | |
JPS5690627A (en) | Semiconductor circuit | |
US3336518A (en) | Sample and hold circuit | |
EP0403174A3 (en) | Differential amplifying circuit operable at high speed | |
JPS57140029A (en) | Output circuit | |
JPS6453611A (en) | Driver circuit | |
JPH0219651B2 (en) | ||
GB2358097A (en) | A low voltage switched capacitor differential amplifier with improved dynamic range | |
SU1314440A1 (en) | Differential amplifier | |
JPS58179023A (en) | Analog switch device and sample holding device using said switch device | |
JPS5769590A (en) | Segnal voltage detecting and amplifying circuit | |
JPS55132130A (en) | Tri-state input circuit | |
JPS6451718A (en) | Counter circuit | |
JPS5516540A (en) | Pulse detection circuit | |
JPS54154255A (en) | Amplifier circuit | |
JPS53126284A (en) | Semiconductor integrated circuit | |
KR930006747Y1 (en) | Voltage increasing circuit for mos | |
SU917306A1 (en) | Flip-flop | |
SU841058A1 (en) | Device for storing and retrieval of information | |
JPS5715295A (en) | Sample holding circuit | |
JPS5741040A (en) | Interstage coupling method of electronic circuit |