JPS5731147A - Method and apparatus for aging of semiconductor device - Google Patents

Method and apparatus for aging of semiconductor device

Info

Publication number
JPS5731147A
JPS5731147A JP10658380A JP10658380A JPS5731147A JP S5731147 A JPS5731147 A JP S5731147A JP 10658380 A JP10658380 A JP 10658380A JP 10658380 A JP10658380 A JP 10658380A JP S5731147 A JPS5731147 A JP S5731147A
Authority
JP
Japan
Prior art keywords
aging
chip
constitution
sent
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10658380A
Other languages
Japanese (ja)
Other versions
JPS6138855B2 (en
Inventor
Hiroshi Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10658380A priority Critical patent/JPS5731147A/en
Publication of JPS5731147A publication Critical patent/JPS5731147A/en
Publication of JPS6138855B2 publication Critical patent/JPS6138855B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To appropriately apply aging, by a method wherein a semiconductor device connected to a lead frame is sent through sending holes, and a predetermined voltage is applied after positioning, and local heating is also applied. CONSTITUTION:An Si chip 6 connected to a film carrier 3 is exactly positioned on a rail 12 by a sprocket 13 using perforations 1. Spring contactors 20 in a contact mechanism 15 is contacted with the external leads of a lead frame 4 and pressed to a rail surface 12, and a voltage is applied to the chip 6. The air is sent to glass tubes 17 containing heaters 18 to spray a high-temperature fluid 16, and predetermined aging is performed by maintaing the chip 6 at high temperatures. By said constitution, sufficient thermal aging can be applied without any influence by contraction and expansion by the heat of the film carrier, and a highly reliable device can be obtained.
JP10658380A 1980-08-01 1980-08-01 Method and apparatus for aging of semiconductor device Granted JPS5731147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10658380A JPS5731147A (en) 1980-08-01 1980-08-01 Method and apparatus for aging of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10658380A JPS5731147A (en) 1980-08-01 1980-08-01 Method and apparatus for aging of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5731147A true JPS5731147A (en) 1982-02-19
JPS6138855B2 JPS6138855B2 (en) 1986-09-01

Family

ID=14437222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10658380A Granted JPS5731147A (en) 1980-08-01 1980-08-01 Method and apparatus for aging of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5731147A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01229947A (en) * 1988-03-10 1989-09-13 Seiko Epson Corp Method for positioning flexible printed circuit board
US5359285A (en) * 1991-07-19 1994-10-25 Sumitomo Electric Industries, Ltd. Method and apparatus for varying temperature and electronic load conditions of a semiconductor device in a burn-in test chamber while performing a burn-in test
JP2010534843A (en) * 2007-10-05 2010-11-11 ムルティテスト・エレクトロニッシェ・ジステーメ・ゲーエムベーハー Plunger for holding and moving electronic components, especially IC

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109834880B (en) * 2019-01-09 2021-10-22 南阳柯丽尔科技有限公司 Aging rack and method for aging thermosensitive film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01229947A (en) * 1988-03-10 1989-09-13 Seiko Epson Corp Method for positioning flexible printed circuit board
US5359285A (en) * 1991-07-19 1994-10-25 Sumitomo Electric Industries, Ltd. Method and apparatus for varying temperature and electronic load conditions of a semiconductor device in a burn-in test chamber while performing a burn-in test
JP2010534843A (en) * 2007-10-05 2010-11-11 ムルティテスト・エレクトロニッシェ・ジステーメ・ゲーエムベーハー Plunger for holding and moving electronic components, especially IC
US8232815B2 (en) 2007-10-05 2012-07-31 Multitest Elektronische Systeme Gmbh Plunger for holding and moving electronic components in particular ICS

Also Published As

Publication number Publication date
JPS6138855B2 (en) 1986-09-01

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