JPS5728489A - Colour signal processing circuit - Google Patents

Colour signal processing circuit

Info

Publication number
JPS5728489A
JPS5728489A JP10252380A JP10252380A JPS5728489A JP S5728489 A JPS5728489 A JP S5728489A JP 10252380 A JP10252380 A JP 10252380A JP 10252380 A JP10252380 A JP 10252380A JP S5728489 A JPS5728489 A JP S5728489A
Authority
JP
Japan
Prior art keywords
output
signal
component
carrier chrominance
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10252380A
Other languages
Japanese (ja)
Inventor
Shuzo Nojima
Yoshihiro Arakawa
Takaaki Nishiseto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10252380A priority Critical patent/JPS5728489A/en
Publication of JPS5728489A publication Critical patent/JPS5728489A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/642—Multi-standard receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To reproduce PAL and NTSC system without using selector switches, by using the characteristic of a carrier chrominance signal and the polarity of 1H delay device output and constituting the circuit with a subtractor, inverter and adder. CONSTITUTION:At the input of PAL system carrier chrominance signal, the phase of an output signal of a carrier chrominance signal amplifier 3 is inverted for (R-Y) axis in every 1H. In the output of an adder 5, the component via a 1H delay device 4 and the component not via it are added to be a signal only with (B-Y) component and it is applied to a (B-Y) demodulator 10. The output of a subtractor 6 is a (R-Y) component in which it is inverted in every 1H, this signal passes through an inverter 7 to be a signal not inverted in every 1H, the output of an adder 23 is inputted to a (R-Y) demodulator 11 to output the (R-Y) component. At the input of NTSC system carrier chrominance signal, the output of the adders 5, 23 is inputted to a the demodulators 10, 11 to demodulate the (B-Y) and (R-Y) components.
JP10252380A 1980-07-28 1980-07-28 Colour signal processing circuit Pending JPS5728489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10252380A JPS5728489A (en) 1980-07-28 1980-07-28 Colour signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10252380A JPS5728489A (en) 1980-07-28 1980-07-28 Colour signal processing circuit

Publications (1)

Publication Number Publication Date
JPS5728489A true JPS5728489A (en) 1982-02-16

Family

ID=14329690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10252380A Pending JPS5728489A (en) 1980-07-28 1980-07-28 Colour signal processing circuit

Country Status (1)

Country Link
JP (1) JPS5728489A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080639A (en) * 1983-10-07 1985-05-08 株式会社大林組 Attachment of insert stud

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080639A (en) * 1983-10-07 1985-05-08 株式会社大林組 Attachment of insert stud

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