JPS5727331A - Series signal reception system - Google Patents

Series signal reception system

Info

Publication number
JPS5727331A
JPS5727331A JP10146580A JP10146580A JPS5727331A JP S5727331 A JPS5727331 A JP S5727331A JP 10146580 A JP10146580 A JP 10146580A JP 10146580 A JP10146580 A JP 10146580A JP S5727331 A JPS5727331 A JP S5727331A
Authority
JP
Japan
Prior art keywords
circuit
storage
data
connects
system bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10146580A
Other languages
Japanese (ja)
Inventor
Tokuo Matsushita
Tsunehisa Enoki
Mitsuo Saijo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10146580A priority Critical patent/JPS5727331A/en
Publication of JPS5727331A publication Critical patent/JPS5727331A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To store received data without exclusively using a system bus by performing storing and reading out while successively changing over the two storage circuits prepared for storage only of the received data by every received data. CONSTITUTION:The 1st data of a series signal is inputted from a terminal SD to a series to parallel conversion circuit 1, from which parallel data is outputted. It is stored into the storage address of a storage circuit 3 assigned by a storage address generating circuit 6 through a selection circuit 2. Upon completion of the storage of the 1st data, the circuit 2 connects the output of the circuit 1 and a storage circuit 6 to a storage circuit 4, and a selection circuit 5 connects a system bus terminal Sb to the circuit 3. When the 2nd data is inputted, it is stored in the storing address of the circuit 4 assigned by the circuit 6 through the circuit 2. Upon completion of the storage of the 2nd data, the circuit 2 connects the output of the circuit 1 and the circuit 6 to the circuit 3 and the circuit 5 connects to the circuit 4 by the system bus terminal Sb.
JP10146580A 1980-07-24 1980-07-24 Series signal reception system Pending JPS5727331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10146580A JPS5727331A (en) 1980-07-24 1980-07-24 Series signal reception system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10146580A JPS5727331A (en) 1980-07-24 1980-07-24 Series signal reception system

Publications (1)

Publication Number Publication Date
JPS5727331A true JPS5727331A (en) 1982-02-13

Family

ID=14301454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10146580A Pending JPS5727331A (en) 1980-07-24 1980-07-24 Series signal reception system

Country Status (1)

Country Link
JP (1) JPS5727331A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2648652A1 (en) * 1989-06-19 1990-12-21 Alcatel Business Systems INTERFACE FOR TRANSMISSION AND RECEPTION ACCESS TO THE SYNCHRONOUS TRANSMISSION MEDIUM OF A DISTRIBUTED SWITCHING NETWORK

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2648652A1 (en) * 1989-06-19 1990-12-21 Alcatel Business Systems INTERFACE FOR TRANSMISSION AND RECEPTION ACCESS TO THE SYNCHRONOUS TRANSMISSION MEDIUM OF A DISTRIBUTED SWITCHING NETWORK
US5084872A (en) * 1989-06-19 1992-01-28 Alcatel Business Systems Interface for transmit and receive mode access to the synchronous transmission medium of a distributed switching network

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