JPS572521A - Forming method for self-alignment multilayer wire - Google Patents
Forming method for self-alignment multilayer wireInfo
- Publication number
- JPS572521A JPS572521A JP7554680A JP7554680A JPS572521A JP S572521 A JPS572521 A JP S572521A JP 7554680 A JP7554680 A JP 7554680A JP 7554680 A JP7554680 A JP 7554680A JP S572521 A JPS572521 A JP S572521A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- wire
- self
- patterned
- photo resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 239000002184 metal Substances 0.000 abstract 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract 3
- 238000004544 sputter deposition Methods 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
PURPOSE:To enhance the reliability of a microminiature multilayer wire by burying a metal or an insulator by a bias sputtering method in the recesses of a substrate, thereby suppressing the disconnection and the shortcircuitting of the wire. CONSTITUTION:An oxidized film 42 is formed on a silicon substrate 41, a photo resist is patterned on a metal 43 to become a wire formed by sputtering on the entire surface of the substrate, and with the photo resist thus patterned as a mask the metal 43 is patterned. A bias sputtering is performed thereon to equalize the surface of the metal 43 to the surface of an SiO2 film 45, and the exposed photo resist is isolated by etching. Thus, the SiO2 film can be so buried between metallic wires in a self-aligning manner that the surfaces may approximately coincide with one another. When these steps are repeated, a multilayer wire can be formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7554680A JPS572521A (en) | 1980-06-06 | 1980-06-06 | Forming method for self-alignment multilayer wire |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7554680A JPS572521A (en) | 1980-06-06 | 1980-06-06 | Forming method for self-alignment multilayer wire |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS572521A true JPS572521A (en) | 1982-01-07 |
Family
ID=13579298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7554680A Pending JPS572521A (en) | 1980-06-06 | 1980-06-06 | Forming method for self-alignment multilayer wire |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS572521A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6324625A (en) * | 1986-07-16 | 1988-02-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JPS6328704A (en) * | 1986-07-23 | 1988-02-06 | Ohtsu Tire & Rubber Co Ltd | Radial tyre |
-
1980
- 1980-06-06 JP JP7554680A patent/JPS572521A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6324625A (en) * | 1986-07-16 | 1988-02-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JPS6328704A (en) * | 1986-07-23 | 1988-02-06 | Ohtsu Tire & Rubber Co Ltd | Radial tyre |
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