JPS5723419B2 - - Google Patents
Info
- Publication number
- JPS5723419B2 JPS5723419B2 JP13535380A JP13535380A JPS5723419B2 JP S5723419 B2 JPS5723419 B2 JP S5723419B2 JP 13535380 A JP13535380 A JP 13535380A JP 13535380 A JP13535380 A JP 13535380A JP S5723419 B2 JPS5723419 B2 JP S5723419B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
- H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Local Oxidation Of Silicon (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7002384.A NL159817B (nl) | 1966-10-05 | 1970-02-19 | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56153748A JPS56153748A (en) | 1981-11-27 |
JPS5723419B2 true JPS5723419B2 (enrdf_load_stackoverflow) | 1982-05-18 |
Family
ID=19809379
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50141238A Pending JPS5176087A (enrdf_load_stackoverflow) | 1970-02-19 | 1975-11-27 | |
JP13535380A Granted JPS56153748A (en) | 1970-02-19 | 1980-09-30 | Integrated semiconductor device |
JP58067155A Granted JPS58212148A (ja) | 1970-02-19 | 1983-04-18 | 集積半導体装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50141238A Pending JPS5176087A (enrdf_load_stackoverflow) | 1970-02-19 | 1975-11-27 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58067155A Granted JPS58212148A (ja) | 1970-02-19 | 1983-04-18 | 集積半導体装置 |
Country Status (6)
Country | Link |
---|---|
JP (3) | JPS5176087A (enrdf_load_stackoverflow) |
BE (1) | BE763112R (enrdf_load_stackoverflow) |
BR (1) | BR7101089D0 (enrdf_load_stackoverflow) |
CA (1) | CA920281A (enrdf_load_stackoverflow) |
ES (1) | ES388379A2 (enrdf_load_stackoverflow) |
IT (1) | IT976361B (enrdf_load_stackoverflow) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3386865A (en) * | 1965-05-10 | 1968-06-04 | Ibm | Process of making planar semiconductor devices isolated by encapsulating oxide filled channels |
-
1971
- 1971-02-15 CA CA105325A patent/CA920281A/en not_active Expired
- 1971-02-16 IT IT20622/71A patent/IT976361B/it active
- 1971-02-17 BE BE763112A patent/BE763112R/xx active
- 1971-02-17 BR BR1089/71A patent/BR7101089D0/pt unknown
- 1971-02-17 ES ES388379A patent/ES388379A2/es not_active Expired
-
1975
- 1975-11-27 JP JP50141238A patent/JPS5176087A/ja active Pending
-
1980
- 1980-09-30 JP JP13535380A patent/JPS56153748A/ja active Granted
-
1983
- 1983-04-18 JP JP58067155A patent/JPS58212148A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
IT976361B (it) | 1974-08-20 |
JPS56153748A (en) | 1981-11-27 |
BE763112R (fr) | 1971-08-17 |
JPS6252458B2 (enrdf_load_stackoverflow) | 1987-11-05 |
JPS5176087A (enrdf_load_stackoverflow) | 1976-07-01 |
CA920281A (en) | 1973-01-30 |
BR7101089D0 (pt) | 1973-02-27 |
JPS58212148A (ja) | 1983-12-09 |
ES388379A2 (es) | 1973-06-01 |