IT976361B - Metodo di fabbricazione di un dispo sitivo semiconduttore e dispositivo semiconduttore ottenuto con l ausi lio di tale metodo - Google Patents

Metodo di fabbricazione di un dispo sitivo semiconduttore e dispositivo semiconduttore ottenuto con l ausi lio di tale metodo

Info

Publication number
IT976361B
IT976361B IT20622/71A IT2062271A IT976361B IT 976361 B IT976361 B IT 976361B IT 20622/71 A IT20622/71 A IT 20622/71A IT 2062271 A IT2062271 A IT 2062271A IT 976361 B IT976361 B IT 976361B
Authority
IT
Italy
Prior art keywords
semiconducting
aid
manufacturing
sitive
device obtained
Prior art date
Application number
IT20622/71A
Other languages
English (en)
Italian (it)
Inventor
E Kooi
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NL7002384.A external-priority patent/NL159817B/xx
Application filed by Philips Nv filed Critical Philips Nv
Application granted granted Critical
Publication of IT976361B publication Critical patent/IT976361B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs
    • H10D84/403Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT20622/71A 1970-02-19 1971-02-16 Metodo di fabbricazione di un dispo sitivo semiconduttore e dispositivo semiconduttore ottenuto con l ausi lio di tale metodo IT976361B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7002384.A NL159817B (nl) 1966-10-05 1970-02-19 Werkwijze ter vervaardiging van een halfgeleiderinrichting.

Publications (1)

Publication Number Publication Date
IT976361B true IT976361B (it) 1974-08-20

Family

ID=19809379

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20622/71A IT976361B (it) 1970-02-19 1971-02-16 Metodo di fabbricazione di un dispo sitivo semiconduttore e dispositivo semiconduttore ottenuto con l ausi lio di tale metodo

Country Status (6)

Country Link
JP (3) JPS5176087A (enrdf_load_stackoverflow)
BE (1) BE763112R (enrdf_load_stackoverflow)
BR (1) BR7101089D0 (enrdf_load_stackoverflow)
CA (1) CA920281A (enrdf_load_stackoverflow)
ES (1) ES388379A2 (enrdf_load_stackoverflow)
IT (1) IT976361B (enrdf_load_stackoverflow)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels

Also Published As

Publication number Publication date
JPS5723419B2 (enrdf_load_stackoverflow) 1982-05-18
JPS56153748A (en) 1981-11-27
CA920281A (en) 1973-01-30
BR7101089D0 (pt) 1973-02-27
JPS6252458B2 (enrdf_load_stackoverflow) 1987-11-05
JPS58212148A (ja) 1983-12-09
BE763112R (fr) 1971-08-17
JPS5176087A (enrdf_load_stackoverflow) 1976-07-01
ES388379A2 (es) 1973-06-01

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