JPS57212678A - Buffer storage device - Google Patents

Buffer storage device

Info

Publication number
JPS57212678A
JPS57212678A JP56098013A JP9801381A JPS57212678A JP S57212678 A JPS57212678 A JP S57212678A JP 56098013 A JP56098013 A JP 56098013A JP 9801381 A JP9801381 A JP 9801381A JP S57212678 A JPS57212678 A JP S57212678A
Authority
JP
Japan
Prior art keywords
address
write
stored
memory
significance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56098013A
Other languages
English (en)
Japanese (ja)
Other versions
JPS622341B2 (enExample
Inventor
Koichi Tsukizoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56098013A priority Critical patent/JPS57212678A/ja
Publication of JPS57212678A publication Critical patent/JPS57212678A/ja
Publication of JPS622341B2 publication Critical patent/JPS622341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56098013A 1981-06-24 1981-06-24 Buffer storage device Granted JPS57212678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56098013A JPS57212678A (en) 1981-06-24 1981-06-24 Buffer storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56098013A JPS57212678A (en) 1981-06-24 1981-06-24 Buffer storage device

Publications (2)

Publication Number Publication Date
JPS57212678A true JPS57212678A (en) 1982-12-27
JPS622341B2 JPS622341B2 (enExample) 1987-01-19

Family

ID=14207919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56098013A Granted JPS57212678A (en) 1981-06-24 1981-06-24 Buffer storage device

Country Status (1)

Country Link
JP (1) JPS57212678A (enExample)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136042A (enExample) * 1974-09-24 1976-03-26 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136042A (enExample) * 1974-09-24 1976-03-26 Hitachi Ltd

Also Published As

Publication number Publication date
JPS622341B2 (enExample) 1987-01-19

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