JPS57207966A - Information recorder - Google Patents
Information recorderInfo
- Publication number
- JPS57207966A JPS57207966A JP9321381A JP9321381A JPS57207966A JP S57207966 A JPS57207966 A JP S57207966A JP 9321381 A JP9321381 A JP 9321381A JP 9321381 A JP9321381 A JP 9321381A JP S57207966 A JPS57207966 A JP S57207966A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- writing
- circuit
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To relieve the limitation of the length of an interface cable between a recorder and a controller, by temporarily accumulating writing data in a memory by receiving them in advance, and recording them by successively reading out them. CONSTITUTION:When a write mode signal is generated from a writing controlling circuit 6 and a recorder starts its writing operation, a data request signal is sent from the circuit 6 to a controller, and a data deliver signal of one byte one byte supplied from the controller is planted in a memory 2 through a receiving circuit 1. At the same time, a memory writing address controlling circuit 3 counts the received data deliver signal and updates a memory writing address to be written in the memory 2. Whenever data are read out from the memory 2, a data readout address of the memory 2 is updated by a memory reading address circuit 4. The data and read out from the memory 2 are sent to a recording section through a writing circuit 5.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9321381A JPS57207966A (en) | 1981-06-17 | 1981-06-17 | Information recorder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9321381A JPS57207966A (en) | 1981-06-17 | 1981-06-17 | Information recorder |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57207966A true JPS57207966A (en) | 1982-12-20 |
Family
ID=14076280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9321381A Pending JPS57207966A (en) | 1981-06-17 | 1981-06-17 | Information recorder |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57207966A (en) |
-
1981
- 1981-06-17 JP JP9321381A patent/JPS57207966A/en active Pending
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