JPS57203124A - Selecting system for transfer bus - Google Patents
Selecting system for transfer busInfo
- Publication number
- JPS57203124A JPS57203124A JP8917881A JP8917881A JPS57203124A JP S57203124 A JPS57203124 A JP S57203124A JP 8917881 A JP8917881 A JP 8917881A JP 8917881 A JP8917881 A JP 8917881A JP S57203124 A JPS57203124 A JP S57203124A
- Authority
- JP
- Japan
- Prior art keywords
- transfer
- request
- bus
- requests
- transfer request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To efficiently perform data transmission, by enabling a transfer bus controller to reference a transfer request directly not through a transfer schedule, through cueing of the transfer request as required. CONSTITUTION:When a transfer request is received from transfer request devices 11-13, a transfer schedule device 21 informs each request to a bus controller A31, a device B32 and a device C33, and a transfer bus controller starts data transfer by using a trnsfer bus A41, a bus A42 and a bus C43. If other transfer requests are made from transfer request devices 14 and 15 during the transfer as mentioned above, the device 21 cues the requests to a cue pointer 22. When the data transfer under the present processing is finished the controllers 31-33 pick up the transfer request from the head of the cue pointer 22, starts the data transfer of the transfer requests and repeat the processings until the cue is vacant.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8917881A JPS57203124A (en) | 1981-06-10 | 1981-06-10 | Selecting system for transfer bus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8917881A JPS57203124A (en) | 1981-06-10 | 1981-06-10 | Selecting system for transfer bus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57203124A true JPS57203124A (en) | 1982-12-13 |
Family
ID=13963505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8917881A Pending JPS57203124A (en) | 1981-06-10 | 1981-06-10 | Selecting system for transfer bus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57203124A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60134366A (en) * | 1983-12-21 | 1985-07-17 | Hitachi Ltd | Direct memory access address control system |
JPS60168256A (en) * | 1984-02-10 | 1985-08-31 | Hitachi Ltd | Address management system of various direct memory access |
JPS60181862A (en) * | 1984-02-29 | 1985-09-17 | Hitachi Ltd | Setting system of dma transfer buffer |
JPS60183665A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
JPS60183666A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
-
1981
- 1981-06-10 JP JP8917881A patent/JPS57203124A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60134366A (en) * | 1983-12-21 | 1985-07-17 | Hitachi Ltd | Direct memory access address control system |
JPS60168256A (en) * | 1984-02-10 | 1985-08-31 | Hitachi Ltd | Address management system of various direct memory access |
JPS60181862A (en) * | 1984-02-29 | 1985-09-17 | Hitachi Ltd | Setting system of dma transfer buffer |
JPS60183665A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
JPS60183666A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
JPH0565896B2 (en) * | 1984-03-02 | 1993-09-20 | Hitachi Ltd |
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