JPS57201937A - Integrated logical circuit device - Google Patents

Integrated logical circuit device

Info

Publication number
JPS57201937A
JPS57201937A JP56085631A JP8563181A JPS57201937A JP S57201937 A JPS57201937 A JP S57201937A JP 56085631 A JP56085631 A JP 56085631A JP 8563181 A JP8563181 A JP 8563181A JP S57201937 A JPS57201937 A JP S57201937A
Authority
JP
Japan
Prior art keywords
logical circuit
shift register
circuit device
circuit
output lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085631A
Other languages
Japanese (ja)
Inventor
Tadanobu Okuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56085631A priority Critical patent/JPS57201937A/en
Publication of JPS57201937A publication Critical patent/JPS57201937A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To test a package easily by dividing the package into LSIs as a combinational circuit and a logical circuit device respectively. CONSTITUTION:An integrated logical circuit device 1 has an internal logical circuit 2, a shift register 3 composed of numbers of flip-flops, and a switching circuit 4 which switches the output of the internal logical circuit 2 and that of the shift register 3 by receiving a test indication signal. The shift register 3 and internal logical circuit 2 operate by receiving input logical signals 9-1-9-N, and their operation results are outputted to output lines 11a-1-11a-L, and 12a- 1-12a-L. When a high-level signal is supplied to a test indication signal line 8a, the switching circuit 4 selects the output lines 12a-1-12a-L of the internal logical circuit 2 and when a low-level signal is supplied, the output lines 11a-1- 11a-L of the shift register 3 are selected.
JP56085631A 1981-06-05 1981-06-05 Integrated logical circuit device Pending JPS57201937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085631A JPS57201937A (en) 1981-06-05 1981-06-05 Integrated logical circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085631A JPS57201937A (en) 1981-06-05 1981-06-05 Integrated logical circuit device

Publications (1)

Publication Number Publication Date
JPS57201937A true JPS57201937A (en) 1982-12-10

Family

ID=13864177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085631A Pending JPS57201937A (en) 1981-06-05 1981-06-05 Integrated logical circuit device

Country Status (1)

Country Link
JP (1) JPS57201937A (en)

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