JPS5710532A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5710532A
JPS5710532A JP8473680A JP8473680A JPS5710532A JP S5710532 A JPS5710532 A JP S5710532A JP 8473680 A JP8473680 A JP 8473680A JP 8473680 A JP8473680 A JP 8473680A JP S5710532 A JPS5710532 A JP S5710532A
Authority
JP
Japan
Prior art keywords
ecl
ttl
phase
group
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8473680A
Other languages
Japanese (ja)
Inventor
Takahisa Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8473680A priority Critical patent/JPS5710532A/en
Publication of JPS5710532A publication Critical patent/JPS5710532A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To match the logical level and to unify the logical function, by providing a circuit which converts the signal voltage and inverts the phase at an input and output part in which the logical signal level is different between the inside and the outside. CONSTITUTION:Since the logical level and the phase of signal are different in TTL and ECL, when the TTL and the ECL are combined, it is required for the level conversion and phase inversion circuit. Thus, to the group A of signals, circuits (a)-(d) having the level conversion and phase inverting functions from the TTL to the ECL are inserted to the input part of LSI and to the B group signals, circuits v, w, x, z having the lever conversion and phase inverting functions from the ECL to the TTL are inserted to the output section of the LSI, and to the D group signals, the same circuits as that of the group B are inserted to the output section of the LSI only for the signals issued externally.
JP8473680A 1980-06-23 1980-06-23 Integrated circuit Pending JPS5710532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8473680A JPS5710532A (en) 1980-06-23 1980-06-23 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8473680A JPS5710532A (en) 1980-06-23 1980-06-23 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS5710532A true JPS5710532A (en) 1982-01-20

Family

ID=13838974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8473680A Pending JPS5710532A (en) 1980-06-23 1980-06-23 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5710532A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193957U (en) * 1984-11-24 1986-06-17
JPH0433394U (en) * 1990-07-12 1992-03-18

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193957U (en) * 1984-11-24 1986-06-17
JPH0427076Y2 (en) * 1984-11-24 1992-06-29
JPH0433394U (en) * 1990-07-12 1992-03-18

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