JPS5719821A - Clearing circuit of random access memory - Google Patents

Clearing circuit of random access memory

Info

Publication number
JPS5719821A
JPS5719821A JP9276280A JP9276280A JPS5719821A JP S5719821 A JPS5719821 A JP S5719821A JP 9276280 A JP9276280 A JP 9276280A JP 9276280 A JP9276280 A JP 9276280A JP S5719821 A JPS5719821 A JP S5719821A
Authority
JP
Japan
Prior art keywords
ram
signal
counter
address
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9276280A
Other languages
Japanese (ja)
Inventor
Takayuki Oshiga
Takashi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9276280A priority Critical patent/JPS5719821A/en
Publication of JPS5719821A publication Critical patent/JPS5719821A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

PURPOSE:To start all-clear of an RAM separately from software, by providing a clock signal oscillating circuit, a counter for counting this clock and scanning in order each address of the RAM, and an FF. CONSTITUTION:After an electric power supply of a system has been turned on, an oscillating circuit 10 starts its oscillation immediately and sends a clock signal CLK to a binary counter 11. The counter 11 counts the signal CLK, outputs its result sequentially to terminals Qo-Qm, and varies an address of an RAM through a buffer 13. In this case, a Q' signal of an FF12 is inputted to a terminal CE of the RAM9, also data inputs Do-Dm of the RAM are made ''0'' through a bubber 14, and a terminal WE input is made to a write state. As a result, an address of the RAM is initialized since an input data ''0'' is written extending over the whole area. When a selecting signal of an RAM area by software comes, the FF is reversed, the oscillator 10 and the counter 11 are reset by a Q signal, and control of the RAM is transferred to a signal which has been sent out from a CPU.
JP9276280A 1980-07-09 1980-07-09 Clearing circuit of random access memory Pending JPS5719821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9276280A JPS5719821A (en) 1980-07-09 1980-07-09 Clearing circuit of random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9276280A JPS5719821A (en) 1980-07-09 1980-07-09 Clearing circuit of random access memory

Publications (1)

Publication Number Publication Date
JPS5719821A true JPS5719821A (en) 1982-02-02

Family

ID=14063431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9276280A Pending JPS5719821A (en) 1980-07-09 1980-07-09 Clearing circuit of random access memory

Country Status (1)

Country Link
JP (1) JPS5719821A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63311551A (en) * 1987-06-15 1988-12-20 Fujitsu Ltd Memory initializing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63311551A (en) * 1987-06-15 1988-12-20 Fujitsu Ltd Memory initializing system

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