JPS57192122A - Signal generating circuit - Google Patents

Signal generating circuit

Info

Publication number
JPS57192122A
JPS57192122A JP56077304A JP7730481A JPS57192122A JP S57192122 A JPS57192122 A JP S57192122A JP 56077304 A JP56077304 A JP 56077304A JP 7730481 A JP7730481 A JP 7730481A JP S57192122 A JPS57192122 A JP S57192122A
Authority
JP
Japan
Prior art keywords
impedance
output terminal
trs
constitution
mos transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56077304A
Other languages
Japanese (ja)
Inventor
Yoji Yasuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56077304A priority Critical patent/JPS57192122A/en
Publication of JPS57192122A publication Critical patent/JPS57192122A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To generate a signal with a prescribed time width at all times, independently of the number of input signals changed at the same time, by connecting each one end of driving MOS transistors to ground potential via an impedance element. CONSTITUTION:Between an output terminal 13 and a ground potential supply terminal 14, driving MOS transistors (TR)s 151-15n taking each pulse as the gate input in parallel connection are connected in series with a resistive element 19. With this constitution, the impedance of the output terminal 13 in the discharge path is determined with the impedance of an element 19 rather than with the impedance of the TRs 151-15n, and the impedance is independent of the number of the TRs at on-state at the same time and the potential drop of the output terminal 13 can be almost at a prescribed level. Thus, the time width in which the output of an inverter 18 obtained by shaping the waveform of the potential of the output terminal 13 is at a high level, can be kept constant.
JP56077304A 1981-05-21 1981-05-21 Signal generating circuit Pending JPS57192122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56077304A JPS57192122A (en) 1981-05-21 1981-05-21 Signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56077304A JPS57192122A (en) 1981-05-21 1981-05-21 Signal generating circuit

Publications (1)

Publication Number Publication Date
JPS57192122A true JPS57192122A (en) 1982-11-26

Family

ID=13630163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56077304A Pending JPS57192122A (en) 1981-05-21 1981-05-21 Signal generating circuit

Country Status (1)

Country Link
JP (1) JPS57192122A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0206405A2 (en) * 1985-06-17 1986-12-30 Koninklijke Philips Electronics N.V. Nor gate with logical low output clamp
US5512847A (en) * 1983-01-31 1996-04-30 Hitachi, Ltd. BiCMOS tri-state output driver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512847A (en) * 1983-01-31 1996-04-30 Hitachi, Ltd. BiCMOS tri-state output driver
EP0206405A2 (en) * 1985-06-17 1986-12-30 Koninklijke Philips Electronics N.V. Nor gate with logical low output clamp

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