JPS57189236A - Information reading system - Google Patents

Information reading system

Info

Publication number
JPS57189236A
JPS57189236A JP56073389A JP7338981A JPS57189236A JP S57189236 A JPS57189236 A JP S57189236A JP 56073389 A JP56073389 A JP 56073389A JP 7338981 A JP7338981 A JP 7338981A JP S57189236 A JPS57189236 A JP S57189236A
Authority
JP
Japan
Prior art keywords
registers
bits
bit
outputs
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56073389A
Other languages
Japanese (ja)
Other versions
JPS6044715B2 (en
Inventor
Noboru Kuchitsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56073389A priority Critical patent/JPS6044715B2/en
Publication of JPS57189236A publication Critical patent/JPS57189236A/en
Publication of JPS6044715B2 publication Critical patent/JPS6044715B2/en
Expired legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To enable reading of huge counting values with simple constitution, by selecting the output of n sets of registers in cascade connection at n bits of a register of n+1 bits, outputting the result to a common bus and writing it at the n+1-th bit. CONSTITUTION:Outputs of n sets of registers 11-1n in cascade connection are connected to a common bus 14. A pulse is sequentially given to a shift input T of an n+1-bit counter 21 every time an output request signal R is given, selection signals S1-Sn are applied from the outputs of the 1st-n-th bits and the counting values of the corresponding registers 11-1n are transmitted to the bus 14. During this operation, the (n+1)-th bit output signal Q of the counter 21 is 0 and the reception of a succeeding input pulse Pin is inhibited by an AND gate. When all data of the registers 11-1n are picked up, the signal Q is switched to 1 by an EOR gate 22 and the next input pulse Pin is read to the registers 11-1n sequentially.
JP56073389A 1981-05-18 1981-05-18 Information reading method Expired JPS6044715B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56073389A JPS6044715B2 (en) 1981-05-18 1981-05-18 Information reading method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56073389A JPS6044715B2 (en) 1981-05-18 1981-05-18 Information reading method

Publications (2)

Publication Number Publication Date
JPS57189236A true JPS57189236A (en) 1982-11-20
JPS6044715B2 JPS6044715B2 (en) 1985-10-04

Family

ID=13516785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56073389A Expired JPS6044715B2 (en) 1981-05-18 1981-05-18 Information reading method

Country Status (1)

Country Link
JP (1) JPS6044715B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0428474Y2 (en) * 1986-07-31 1992-07-09

Also Published As

Publication number Publication date
JPS6044715B2 (en) 1985-10-04

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