JPS6044715B2 - Information reading method - Google Patents

Description

[Detailed description of the invention] The present invention relates to an information reading method.

For example, systems that use the number of pulses output from an external sensor as input data are often found.

In online data processing systems and the like, the input data is further processed by a processor. By the way, processors that handle such input data generally handle the input data as information in word units, and usually the word units are fixed in advance, such as 8 bits or 16 bits. is normal.

Therefore, when the number of pulses exceeds 8 bits or 16 bits in binary representation, the processor can no longer handle the number of pulses as information in units of words. Therefore, in order to eliminate such inconveniences, the present applicant came up with a reading method that will be described in detail later.

Roughly speaking, this reading method involves arranging multiple registers in parallel, connecting their outputs in a bus format, and accessing the multiple registers sequentially to read out pulse count values in word units in a time-division manner. That is what it is. However, as will be explained later, this method requires a decoder circuit to select each register and a reception inhibit circuit to inhibit reception of input pulses from the outside while sequentially reading from multiple registers. In addition to the second drawback that when forming the decoder circuit, as the number of the plurality of registers increases, the structure thereof becomes increasingly complex. Therefore, an object of the present invention is to propose an information reading method capable of eliminating the above-mentioned drawbacks.

In accordance with the above object, the present invention connects the respective outputs of n cascaded registers to a common bus, sequentially selects the n registers by each bit output of the n11-bit capacity register, and transmits information. Output to the common bus and output to the n
The present invention is characterized in that information can be written into the n registers only when the most significant or least significant bit of the +1 bit register is being output.

FIG. 1 is a block diagram showing an example of a conventional reading method.

In this figure, Pin is a series of input pulses to be counted, which are supplied during a predetermined period between, for example, one interrupt instruction and the i-th interrupt instruction. This series of input pulses Pin is first applied to the input IN of the first register 11 via an AND gate. This first register 11 outputs, for example, a pulse count value for one word. Now, suppose input pulse Pi
There is no problem if the number n can be sufficiently displayed in one word, but if the number becomes huge, it cannot be counted in a single register. Therefore, a plurality of registers are connected in series like a second register 12, a third register 13, . Input pulses Pjn are counted in correspondence with digits.
When an external output request signal R is applied, the contents of these register groups are supplied to the bus 14 in a time-division manner. Time-divisionally means that for each word corresponding to each register,
This means that the data is serially supplied to a processor (not shown). In this way, a huge number of counts can be converted into word-based information that is easy for the processor to process. By the way, when performing the above operation, a first means for outputting register selection signals Sl, S2, S3 to Sn for sequentially selecting the register groups 11 to 1n, and a first means for outputting register selection signals Sl, S2, S3 to Sn for sequentially selecting the register groups 11 to 1n, and a first means for outputting register selection signals Sl, S2, S3 to Sn for sequentially selecting the register groups 11 to 1n, and a first means for outputting register selection signals Sl, S2, S3 to Sn for sequentially selecting the register groups 11 to 1n, and a first means for outputting register selection signals Sl, S2, S3 to Sn for sequentially selecting the register groups 11 to 1n, and A second means is required for generating a signal Q for permitting the reception of the input pulse Pin when the output is on the bus 14, while inhibiting the reception when the output is being sent to the bus 14.

Note that input pulses Pl that arrive while reception is prohibited
Compensation for n is also necessary, but since this problem is not the essence of the present invention, its description will be omitted. This first means is shown as a decoder circuit 15 in FIG. 1, and the second means is shown as an input control circuit 16. The decoder circuit 15 receives a series of address data Da from the outside, for example from the processor, and outputs a corresponding register selection signal S1.
~Sn are output sequentially and each register is selected. Further, the input control circuit 16 outputs the signal Q depending on the presence or absence of the address data Da. That is, the logic level of the signal Q is set to ``0'' when address data is present, and ``1'' when there is no address data. By the way, in such a configuration, not only the circuits 15 and 16 are indispensable, but also the address data D. In addition, as the number of registers 11 to 1a increases, the hardware of the circuit 15 increases and becomes more complex.

Therefore, the present invention proposes a method that can alleviate such disadvantages that the circuit of FIG. 1 has. FIG. 2 is a block diagram showing an embodiment of the reading method according to the present invention. Further, FIG. 3 is a waveform diagram showing the main parts of the signals in FIG. 2.
In FIG. 2, the same components as in FIG. 1 are designated with the same reference numbers or symbols. Therefore, a register with a counting function (hereinafter referred to as a counter)
21 and an EOR (ExcILlsiveOR) gate 22 are newly introduced circuits, and are composed only of relatively simple hardware. Moreover, address data D
a is unnecessary. The counter 21 is the first bit on the least significant bit side.
Bit output 1 to most significant bit side ``nth bit output 6''
are present corresponding to each of the registers 11 to 1n, and the (n+1)th bit output 8 is provided for one more bit. These first to (n+1)th bit outputs have, for example, logic "1".
Each time there is an input to the shift input T, "" appears alternatively while being shifted upward.

Signals R, T, Sl, S2, S3, Sn in FIG.
The waveforms of data on Q and bus 14 are shown in (a) in Figure 3.
- (1) Column (excluding column (f)) are shown in parentheses. (f
) column is the waveform of the signal from the (n-1)th bit output (not shown) of the counter 21. In addition, the average in this figure is E.
The delay time in the OR gate 22, DS is the counter 21
The delay times are shown respectively. Further, the dashed dotted line in this figure indicates that the scale of the time axis is different before and after the line.
In other words, the time axis is expanded from the dashed line.
This is to make it easier to understand how the signal Q is output by the n-th bit output. Referring to FIG. 3 (and FIG. 2), each time the output request signal R is supplied, the soft input T is sequentially applied to the register selection signals Sl, S2,
S3... is supplied from each bit output, causing the corresponding registers 11, 12, 13... to send out the count values.

These are the count value data Dl, D2, D3 and
It appears as... During this time, the logic of the signal Q ((n+1)th bit output of the counter 21) is ``0'', and reception of the subsequent input pulse Pin is prohibited by the AND gate. This is to prevent the contents from changing while data is being taken out onto the bus 14.
However, after all these data are taken out, the logic of the signal Q must be changed to ゜゛1゛ and the next input pulse Pin must be received. For this reason, in the circuit of Fig. 1, a special circuit 16
However, the present invention provides the n-th and (n+1)-th
By cleverly utilizing the bit output and the EOR gate 22, the signal Q can be switched to "1" as shown in column (h) without introducing such a special circuit. As explained above, according to the present invention, functions equivalent to the circuit shown in FIG. 1 can be realized with as simple a configuration as possible.

Note that the present invention can also be applied to inputting a series of outputs from a counter (not shown) to each register, and sequentially outputting them from each register to a bus.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional reading method;
3 is a block diagram showing an embodiment of the reading system according to the present invention, and FIG. 3 is a waveform diagram showing main signals in FIG. 2. 11, 12~1n...Register, 14...
...Bus, 21...Counter, 22...
EOR gate.

Claims (1)

[Claims] 1 Connect the outputs of each of the n registers connected in cascade to a common bus, sequentially select the n registers by each bit output of the register with a capacity of n+1 bits, and output information to the common bus. , only when the most significant or least significant bit of the n+1 bit register is output.
An information reading method characterized in that information can be written into the n registers.