JPS57187744A - Holding circuit for digital maximum and minimum values - Google Patents
Holding circuit for digital maximum and minimum valuesInfo
- Publication number
- JPS57187744A JPS57187744A JP7168081A JP7168081A JPS57187744A JP S57187744 A JPS57187744 A JP S57187744A JP 7168081 A JP7168081 A JP 7168081A JP 7168081 A JP7168081 A JP 7168081A JP S57187744 A JPS57187744 A JP S57187744A
- Authority
- JP
- Japan
- Prior art keywords
- value
- converter
- digital
- output
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
Abstract
PURPOSE:To hold stably a held value for a long time with simple constitution, by comparing the digital output value of an A/D converter with the digital output value of a storage circuit and updating the stored digital value when the output value of the converter is larger than the output value of the storage circuit. CONSTITUTION:An A/D converter 11 converts digitally an analog input signal AIN synchronously with the rise of a conversion command signal STC from the external and outputs a digital value of plural bits in parallel. When the digital value of plural bits of the converter 11 is outputted, a conversion end signal EOC is supplied to one input terminal A of a comparator 13 and a register 12. The output of the converter 11 is stored in the register 12 synchronously with the rise of a synchronizing signal CP, and the stored digital value is supplied to the other input terminal B of the comparator 13 and a decode driving circuit 14. The comparator 13 compares both digital values with each other and outputs a high-level comparison signal COMP when the value inputted to the terminal A is larger than that inputted to the terminal B. The output of the converter 11 is stored in the register synchronously with this output to update stored contents of the register 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7168081A JPS57187744A (en) | 1981-05-13 | 1981-05-13 | Holding circuit for digital maximum and minimum values |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7168081A JPS57187744A (en) | 1981-05-13 | 1981-05-13 | Holding circuit for digital maximum and minimum values |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57187744A true JPS57187744A (en) | 1982-11-18 |
Family
ID=13467518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7168081A Pending JPS57187744A (en) | 1981-05-13 | 1981-05-13 | Holding circuit for digital maximum and minimum values |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57187744A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63292227A (en) * | 1987-05-25 | 1988-11-29 | Matsushita Electric Ind Co Ltd | Arithmetic circuit |
| JPH08132U (en) * | 1992-06-10 | 1996-01-23 | 大和製衡株式会社 | Stick-on strain gauge |
| US9987640B2 (en) | 2013-02-11 | 2018-06-05 | Dürr Systems GmbH | Coating agent deflection by a coating device |
-
1981
- 1981-05-13 JP JP7168081A patent/JPS57187744A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63292227A (en) * | 1987-05-25 | 1988-11-29 | Matsushita Electric Ind Co Ltd | Arithmetic circuit |
| JPH08132U (en) * | 1992-06-10 | 1996-01-23 | 大和製衡株式会社 | Stick-on strain gauge |
| US9987640B2 (en) | 2013-02-11 | 2018-06-05 | Dürr Systems GmbH | Coating agent deflection by a coating device |
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