JPS57187727A - Control system for channel buffer memory - Google Patents

Control system for channel buffer memory

Info

Publication number
JPS57187727A
JPS57187727A JP7188981A JP7188981A JPS57187727A JP S57187727 A JPS57187727 A JP S57187727A JP 7188981 A JP7188981 A JP 7188981A JP 7188981 A JP7188981 A JP 7188981A JP S57187727 A JPS57187727 A JP S57187727A
Authority
JP
Japan
Prior art keywords
tag
address
flag
partial
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7188981A
Other languages
Japanese (ja)
Inventor
Satoshi Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7188981A priority Critical patent/JPS57187727A/en
Publication of JPS57187727A publication Critical patent/JPS57187727A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Abstract

PURPOSE:To shorten the occupation time of a main storage part (MM) of a channel buffer memory (CHB) by storing partial store data from a channel directly in the main storage. CONSTITUTION:For partial storage by a channel CHP, an address is read out by the system of a request address register REG1 and a tag part TAG and four kind of coincidence circuit EOR perform address comparison. In the partial storage, partial store data are written from the register REG5 directly in a main storage. At this time, when there is a coincident address in the tag part TAG and it shows a block of an effective display (V) flag ''1'' and a modification display (C) flag of ''O'', a TAG write address is sent from the register REG2 to the tag part TAG to write 0 in the V flag of the corresponding block, and it is erased from the tag part TAG, but no processing regarding the tag part TAG is performed in other cases.
JP7188981A 1981-05-13 1981-05-13 Control system for channel buffer memory Pending JPS57187727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7188981A JPS57187727A (en) 1981-05-13 1981-05-13 Control system for channel buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7188981A JPS57187727A (en) 1981-05-13 1981-05-13 Control system for channel buffer memory

Publications (1)

Publication Number Publication Date
JPS57187727A true JPS57187727A (en) 1982-11-18

Family

ID=13473548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7188981A Pending JPS57187727A (en) 1981-05-13 1981-05-13 Control system for channel buffer memory

Country Status (1)

Country Link
JP (1) JPS57187727A (en)

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