JPS57186860A - Variable synchronizing data transmitting device - Google Patents
Variable synchronizing data transmitting deviceInfo
- Publication number
- JPS57186860A JPS57186860A JP56071466A JP7146681A JPS57186860A JP S57186860 A JPS57186860 A JP S57186860A JP 56071466 A JP56071466 A JP 56071466A JP 7146681 A JP7146681 A JP 7146681A JP S57186860 A JPS57186860 A JP S57186860A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- signal
- circuit
- data
- synchronizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4902—Pulse width modulation; Pulse position modulation
Landscapes
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To transmit and receive a data by an optional clock frequency, by arraying in series a clock pulse and a data pulse on the time base, and transmitting and receiving them. CONSTITUTION:A synchronizing pulse C is obtained by inputting a clock frequency A to a monostable multivibrator 1. On the other hand, a data pulse E is obtained by delaying 2 a data signal B and taking AND with the signal C. When this pulse E is delayed 4 and a data pulse F is inputted to an OR circuit 5 together with the signal C, a series synchronizing signal G in which the synchronizing pulse and the data pulse have been arrayed in series on the time base is obtained as an output of the circuit 5. On the other hand, in the receiving part, a signal I is obtained by shaping a receiving waveform H by a monostable multivibrator 7. This signal I is provided to a synchronizing pulse extracting means consisting of a delaying circuit 8, an AND circuit 9, a NOT circuit 10 and an AND circuit 11, by which a synchronizing pulse N is obtained. This pulse N is delayed 12 and is provided to a clock terminal C of a D type FF 14. On the other hand, to an FF 14, an output of a monostable multivibrator 13 is provided, and a reloaded data signal P is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56071466A JPS57186860A (en) | 1981-05-14 | 1981-05-14 | Variable synchronizing data transmitting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56071466A JPS57186860A (en) | 1981-05-14 | 1981-05-14 | Variable synchronizing data transmitting device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57186860A true JPS57186860A (en) | 1982-11-17 |
Family
ID=13461392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56071466A Pending JPS57186860A (en) | 1981-05-14 | 1981-05-14 | Variable synchronizing data transmitting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57186860A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4877705A (en) * | 1972-01-18 | 1973-10-19 | ||
JPS5335404A (en) * | 1976-09-14 | 1978-04-01 | Kouhan Denshi Kougiyou Kk | Information transmission system |
-
1981
- 1981-05-14 JP JP56071466A patent/JPS57186860A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4877705A (en) * | 1972-01-18 | 1973-10-19 | ||
JPS5335404A (en) * | 1976-09-14 | 1978-04-01 | Kouhan Denshi Kougiyou Kk | Information transmission system |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS647252A (en) | Array processing system | |
JPS52127113A (en) | Signal transmitter | |
JPS55161447A (en) | Data transmission system | |
EP0048638A3 (en) | Maximum frequency limiter | |
JPS57186860A (en) | Variable synchronizing data transmitting device | |
JPS5435666A (en) | Timing extraction system | |
JPS5372410A (en) | Signal transmission system | |
JPS5799062A (en) | Reception circuit for data transmission | |
JPS55118248A (en) | Timing extracting circuit | |
JPS5425657A (en) | Waveform conversion circuit | |
JPS53136465A (en) | Pulse generating circuit | |
JPS5525292A (en) | Data reception device | |
JPS5775047A (en) | Timing extracting circuit | |
JPS5544649A (en) | Input control unit | |
JPS53107222A (en) | Mfm demodulation system | |
JPS5372411A (en) | Signal transmission system | |
JPS57201319A (en) | Synchronizing pulse generating circuit | |
JPS5496316A (en) | Digital signal multiple transmission system | |
ES466252A1 (en) | Television signal identification circuit | |
JPS56103560A (en) | Demodulating circuit | |
JPS5773552A (en) | In-step synchronism type receiving circuit | |
JPS5757093A (en) | Sampling clock pulse generating circuit | |
JPS5235674A (en) | Device for generating preset time concidence signal | |
JPS56160162A (en) | Data transmitting system | |
JPS5487412A (en) | Code transferring method |