JPS57201319A - Synchronizing pulse generating circuit - Google Patents

Synchronizing pulse generating circuit

Info

Publication number
JPS57201319A
JPS57201319A JP56086462A JP8646281A JPS57201319A JP S57201319 A JPS57201319 A JP S57201319A JP 56086462 A JP56086462 A JP 56086462A JP 8646281 A JP8646281 A JP 8646281A JP S57201319 A JPS57201319 A JP S57201319A
Authority
JP
Japan
Prior art keywords
rsff
output
terminal
output terminal
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56086462A
Other languages
Japanese (ja)
Inventor
Hiroshi Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56086462A priority Critical patent/JPS57201319A/en
Publication of JPS57201319A publication Critical patent/JPS57201319A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a pulse of a fixed value, by performing resetting of the 1st RSFF which is set by an input signal and the 2nd RSFF which is set by the output of the 1st RSFF with the coincidence of the output of the 2nd RSFF and the inversed signal of a clock pulse. CONSTITUTION:An input signal X is impressed upon a set terminal 1001 of the 1st RSFF 100. An output terminal 100b and the input signal X of the FF 100 and an output which is passed through an inverter 15 of a differentiating circuit 300 which differentiates a clock pulse input Y are connected to an input terminal 200a of the 2nd FSFF 200 through the 1st coincidence circuit 3. An inversed clock output terminal 300c of the differentiating circuit 300 and an output terminal 200b of the 2nd RSFF 200 are connected to each reset terminal 100c and 200c of the 1st and 2nd RSFF 100 and 200 through the 2nd coincidence circuit 7. When this configuration is realized, a pulse signal having a constant width can be obtained surely at an output terminal Z.
JP56086462A 1981-06-04 1981-06-04 Synchronizing pulse generating circuit Pending JPS57201319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56086462A JPS57201319A (en) 1981-06-04 1981-06-04 Synchronizing pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56086462A JPS57201319A (en) 1981-06-04 1981-06-04 Synchronizing pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS57201319A true JPS57201319A (en) 1982-12-09

Family

ID=13887611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56086462A Pending JPS57201319A (en) 1981-06-04 1981-06-04 Synchronizing pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS57201319A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61161013A (en) * 1985-01-08 1986-07-21 Matsushita Electric Ind Co Ltd Synchronous pulse generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61161013A (en) * 1985-01-08 1986-07-21 Matsushita Electric Ind Co Ltd Synchronous pulse generating circuit
JPH0351331B2 (en) * 1985-01-08 1991-08-06 Matsushita Electric Ind Co Ltd

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