JPS57184233A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57184233A
JPS57184233A JP6900781A JP6900781A JPS57184233A JP S57184233 A JPS57184233 A JP S57184233A JP 6900781 A JP6900781 A JP 6900781A JP 6900781 A JP6900781 A JP 6900781A JP S57184233 A JPS57184233 A JP S57184233A
Authority
JP
Japan
Prior art keywords
layer
wiring
aluminum wiring
insulating film
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6900781A
Other languages
Japanese (ja)
Inventor
Hiroyuki Misawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6900781A priority Critical patent/JPS57184233A/en
Publication of JPS57184233A publication Critical patent/JPS57184233A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce parasitic capacitance among mutual wiring layers, and to improve the coating rate of the difference in stages of upper layer wiring by positioning the third wiring layer at a connecting section connecting the first wiring layer and the second wiring layer. CONSTITUTION:The first layer aluminum wiring 51 is connected to the second layer aluminum wiring 54 through the layer connecting aluminum wiring 53 through a layer insulating film opening section 52, and a layer insulating film 63 is positioned in order to interrupt the effect of anodic oxidation on the first layer aluminum wiring 61 when layer connecting aluminum wiring 65 is formed. The first layer aluminum wiring 61 is connected to the second layer aluminum wiring 67 through the layer connecting aluminum wiring 65 through an isulating opening section 64 bored onto the layer insulating film 63 as the upper layer of the first layer aluminum wiring and an anode oxidizing insulator 62, and a layer connecting wiring layer anode oxidizing inuslator 66 is positioned between the first layer aluminum wiring 61 and the second layer aluminum wiring 67 except the connecting section, thus reducing parasitic wiring capacitance.
JP6900781A 1981-05-08 1981-05-08 Semiconductor device Pending JPS57184233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6900781A JPS57184233A (en) 1981-05-08 1981-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6900781A JPS57184233A (en) 1981-05-08 1981-05-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57184233A true JPS57184233A (en) 1982-11-12

Family

ID=13390100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6900781A Pending JPS57184233A (en) 1981-05-08 1981-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57184233A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995008841A1 (en) * 1993-09-20 1995-03-30 Labunov Vladimir A Process for making multilevel interconnections of electronic components

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4941854A (en) * 1972-08-30 1974-04-19
JPS4998587A (en) * 1973-01-22 1974-09-18
JPS5045580A (en) * 1973-08-24 1975-04-23

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4941854A (en) * 1972-08-30 1974-04-19
JPS4998587A (en) * 1973-01-22 1974-09-18
JPS5045580A (en) * 1973-08-24 1975-04-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995008841A1 (en) * 1993-09-20 1995-03-30 Labunov Vladimir A Process for making multilevel interconnections of electronic components

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