JPS57183145A - Data transmitter - Google Patents

Data transmitter

Info

Publication number
JPS57183145A
JPS57183145A JP6697581A JP6697581A JPS57183145A JP S57183145 A JPS57183145 A JP S57183145A JP 6697581 A JP6697581 A JP 6697581A JP 6697581 A JP6697581 A JP 6697581A JP S57183145 A JPS57183145 A JP S57183145A
Authority
JP
Japan
Prior art keywords
circuit
signal
information
amount
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6697581A
Other languages
Japanese (ja)
Inventor
Yukiyoshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6697581A priority Critical patent/JPS57183145A/en
Publication of JPS57183145A publication Critical patent/JPS57183145A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/16Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1682Allocation of channels according to the instantaneous demands of the users, e.g. concentrated multiplexers, statistical multiplexers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To transmit a large amount of data while varying the amount of transmitted information by providing a storage circuit, which corresponds to the amount of transmitted information, on a receiver side. CONSTITUTION:On the basis of the timing of a clock circuit 61, a counter circuit 62 operates. The contents of the counter circuit 62 are decoded by a decoding circuit 63. According to the decoding result, one of driving circuits 64 is selected. The selected driving circuit 64 transfers on-off information on an optional group of contacts 4 and an answer signal SA to a level converting circuit 11. After sending out a synchronizing signal S1, a parallel-serial converting circuit 12 sends out the count value of the counter circuit 62 as an address information signal S3. Then, the external answer signal SA and a data signal S2' consisting of pieces of on-off information on respective contacts are sent out in order. A receiving circuit 21 receives the signals from a transmission line 3 and sends out them to a serial-parallel converting circuit 22, an address discriminating circuit 71, and a timing control circuit 74. The data signal S2' to be stored is sent to a storage circuit 72, where it is stored.
JP6697581A 1981-05-06 1981-05-06 Data transmitter Pending JPS57183145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6697581A JPS57183145A (en) 1981-05-06 1981-05-06 Data transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6697581A JPS57183145A (en) 1981-05-06 1981-05-06 Data transmitter

Publications (1)

Publication Number Publication Date
JPS57183145A true JPS57183145A (en) 1982-11-11

Family

ID=13331527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6697581A Pending JPS57183145A (en) 1981-05-06 1981-05-06 Data transmitter

Country Status (1)

Country Link
JP (1) JPS57183145A (en)

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