JPS57183056A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57183056A
JPS57183056A JP6956481A JP6956481A JPS57183056A JP S57183056 A JPS57183056 A JP S57183056A JP 6956481 A JP6956481 A JP 6956481A JP 6956481 A JP6956481 A JP 6956481A JP S57183056 A JPS57183056 A JP S57183056A
Authority
JP
Japan
Prior art keywords
wiring
forming
concentration
implanted
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6956481A
Other languages
Japanese (ja)
Inventor
Hiromi Sakurai
Yoichi Akasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6956481A priority Critical patent/JPS57183056A/en
Priority to DE19823217026 priority patent/DE3217026A1/en
Publication of JPS57183056A publication Critical patent/JPS57183056A/en
Priority to US06/717,597 priority patent/US4899206A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To eliminate the whiskers generated in case of forming the wiring preventing the wirings from shortcircuiting by a method wherein, when the Al wiring with the high purity is formed on the semiconductor wafer including the device, the impurity ion such as Ar, P, As, Sb and the like is implanted immediately after forming the wiring with the concentration upon the wiring exceeding 5%. CONSTITUTION:The SiO2 film 11 is formed on the Si wafer 10 with the PN joint and said film 11 is coated with the Al metallic wiring 12 with the density of 6.02X10<22>/cm<2> by means of the sputtering. Then the impurity ion such as P<+>, As<+> and the like with the concentration exceeding 5% is implanted in said metallic wiring 12 to the whisker generated inside the wiring 12 in case of forming the wiring 12. Through these procedures, both the density of said wiring 12 and the concentration of the implanted ion are specified to remove the whiskers to be generated. Consequently the shortcircuit between the wirings may be prevented improving the yield and the reliability of the device.
JP6956481A 1981-05-06 1981-05-06 Semiconductor device Pending JPS57183056A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6956481A JPS57183056A (en) 1981-05-06 1981-05-06 Semiconductor device
DE19823217026 DE3217026A1 (en) 1981-05-06 1982-05-06 Semiconductor device
US06/717,597 US4899206A (en) 1981-05-06 1985-04-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6956481A JPS57183056A (en) 1981-05-06 1981-05-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57183056A true JPS57183056A (en) 1982-11-11

Family

ID=13406381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6956481A Pending JPS57183056A (en) 1981-05-06 1981-05-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57183056A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188120A (en) * 1983-03-12 1984-10-25 Ricoh Co Ltd Forming method for thin film
US5040048A (en) * 1988-10-25 1991-08-13 Mitsubishi Denki Kabushiki Kaisha Metal interconnection layer having reduced hillock formation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55158649A (en) * 1979-05-30 1980-12-10 Fujitsu Ltd Manufacture of electrode wiring

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55158649A (en) * 1979-05-30 1980-12-10 Fujitsu Ltd Manufacture of electrode wiring

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188120A (en) * 1983-03-12 1984-10-25 Ricoh Co Ltd Forming method for thin film
US5040048A (en) * 1988-10-25 1991-08-13 Mitsubishi Denki Kabushiki Kaisha Metal interconnection layer having reduced hillock formation

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