JPS57178345A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS57178345A
JPS57178345A JP56062480A JP6248081A JPS57178345A JP S57178345 A JPS57178345 A JP S57178345A JP 56062480 A JP56062480 A JP 56062480A JP 6248081 A JP6248081 A JP 6248081A JP S57178345 A JPS57178345 A JP S57178345A
Authority
JP
Japan
Prior art keywords
layer
substrate
insulation film
peripheral edge
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56062480A
Other languages
Japanese (ja)
Inventor
Kohei Yamada
Hiroshi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56062480A priority Critical patent/JPS57178345A/en
Publication of JPS57178345A publication Critical patent/JPS57178345A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PURPOSE:To prevent an element from deteriorating its electrical characteristics at high temperatures, by making a bonding promotion layer smaller than a lower barrier metal, and leaving its peripheral edge far from an inner edge of insulation film defining a contact window. CONSTITUTION:A P type region 5 is provided at the center of an N type Si substrate 4 to have a shallow P-N junction. The substrate 4 has a cathode 13 on its lower surface and an anode 9 on its upper surface. The anode 9 is formed on a contact window region 7 where a passivation film 14 covering the surface of the substrate 4 is removed partially. It consists of a barrier metal 10 of titanium, a bonding promotion layer 11 of Pd formed thereupon, and a bump electrode 12 of silver formed thereupon, making a triple layer structure. The layer 11 is smaller than the metal 10, and its peripheral edge is far from an inner edge of insulation film 8 on the region 5. Namely, this prevents the Pd layer fast in alloying with Si from existing on the upper part of P type region 5 corresponding to the inner peripheral edge of insulation film 8 high in thermal stress.
JP56062480A 1981-04-27 1981-04-27 Semiconductor element Pending JPS57178345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56062480A JPS57178345A (en) 1981-04-27 1981-04-27 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56062480A JPS57178345A (en) 1981-04-27 1981-04-27 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS57178345A true JPS57178345A (en) 1982-11-02

Family

ID=13201384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56062480A Pending JPS57178345A (en) 1981-04-27 1981-04-27 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS57178345A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205249A (en) * 2007-02-21 2008-09-04 Renesas Technology Corp Method of fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205249A (en) * 2007-02-21 2008-09-04 Renesas Technology Corp Method of fabricating semiconductor device

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