JPS57173766A - Safe operation area measurement for transistor - Google Patents

Safe operation area measurement for transistor

Info

Publication number
JPS57173766A
JPS57173766A JP5895381A JP5895381A JPS57173766A JP S57173766 A JPS57173766 A JP S57173766A JP 5895381 A JP5895381 A JP 5895381A JP 5895381 A JP5895381 A JP 5895381A JP S57173766 A JPS57173766 A JP S57173766A
Authority
JP
Japan
Prior art keywords
pulse
locus
width
added
luminance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5895381A
Other languages
Japanese (ja)
Other versions
JPS63741B2 (en
Inventor
Yoshio Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5895381A priority Critical patent/JPS57173766A/en
Publication of JPS57173766A publication Critical patent/JPS57173766A/en
Publication of JPS63741B2 publication Critical patent/JPS63741B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2607Circuits therefor
    • G01R31/2608Circuits therefor for testing bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To make it possible to have an excellent observation of the locus that is large and occurs when a transistor is overloaded by raising luminance only during a specified width of pulse. CONSTITUTION:X-axis output of a storage oscilloscope 2 is added to a peak detection circuit 3, and when electric current over the level (A) is generated, pulse 2-a is produced. The level (A) can be easily adjusted by a variable resistor 4. The pulse 2a is added to a modulation time adjusting circuit 5 and the width of the pulse 2-a is enlarged as shown in pulse 2-b. This pulse is reversed by an output circuit 6 and added to the luminance modulation shaft of the storage oscilloscope 2 and its luminance is raised during the period of the pulse than other periods to observe loci b and e. The pulse width of the pulse 2-a is shorter than that during a large locus is being generated, so that the pulse width is stretched to a suitable value with a variable resistor 7. With this setup both normal locus and abnormal locus can be measured satisfactorily.
JP5895381A 1981-04-17 1981-04-17 Safe operation area measurement for transistor Granted JPS57173766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5895381A JPS57173766A (en) 1981-04-17 1981-04-17 Safe operation area measurement for transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5895381A JPS57173766A (en) 1981-04-17 1981-04-17 Safe operation area measurement for transistor

Publications (2)

Publication Number Publication Date
JPS57173766A true JPS57173766A (en) 1982-10-26
JPS63741B2 JPS63741B2 (en) 1988-01-08

Family

ID=13099193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5895381A Granted JPS57173766A (en) 1981-04-17 1981-04-17 Safe operation area measurement for transistor

Country Status (1)

Country Link
JP (1) JPS57173766A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101893677A (en) * 2010-07-07 2010-11-24 佛山市蓝箭电子有限公司 Test device and test method of triode under reverse biased safe operating area
CN110221190A (en) * 2019-06-06 2019-09-10 北京工业大学 Power semiconductor safety operation area accurate measurement method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101893677A (en) * 2010-07-07 2010-11-24 佛山市蓝箭电子有限公司 Test device and test method of triode under reverse biased safe operating area
CN110221190A (en) * 2019-06-06 2019-09-10 北京工业大学 Power semiconductor safety operation area accurate measurement method
CN110221190B (en) * 2019-06-06 2021-11-26 北京工业大学 Method for accurately measuring safe working area of power semiconductor device

Also Published As

Publication number Publication date
JPS63741B2 (en) 1988-01-08

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