JPS57172597A - Checking circuit for memory beadout output - Google Patents

Checking circuit for memory beadout output

Info

Publication number
JPS57172597A
JPS57172597A JP56057177A JP5717781A JPS57172597A JP S57172597 A JPS57172597 A JP S57172597A JP 56057177 A JP56057177 A JP 56057177A JP 5717781 A JP5717781 A JP 5717781A JP S57172597 A JPS57172597 A JP S57172597A
Authority
JP
Japan
Prior art keywords
level
output
memory
data
comparators
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56057177A
Other languages
Japanese (ja)
Inventor
Shuichi Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56057177A priority Critical patent/JPS57172597A/en
Publication of JPS57172597A publication Critical patent/JPS57172597A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To securely check whether all bits of an ROM are defective or not, by comparing the output level of data read out of a memory with a high and a low permissible level through a setting circuit for the most inferior readout condition. CONSTITUTION:The output level of data 5 read out of a memory 2 is passed through a setting circuit 11 for the most inferior readout condition and compared with a high permissible level voltage as a low level state and a low permissible level voltage as a high level state by comparators 12 and 13 respectively. When the output level of the data 5 is found to be between the permissible levels from the outputs of the comparators 12 and 13, it is judged by the detection output that the data 5 is an error. For example, said circuit 11, comparators 12 and 13, an EOR gate 14, an OR gate 15, an error FF17, an AND gate 18, and a reference voltage setting circuit 19 are connected as shown in the figure, thus constituting a checking circuit 6.
JP56057177A 1981-04-17 1981-04-17 Checking circuit for memory beadout output Pending JPS57172597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56057177A JPS57172597A (en) 1981-04-17 1981-04-17 Checking circuit for memory beadout output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56057177A JPS57172597A (en) 1981-04-17 1981-04-17 Checking circuit for memory beadout output

Publications (1)

Publication Number Publication Date
JPS57172597A true JPS57172597A (en) 1982-10-23

Family

ID=13048241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56057177A Pending JPS57172597A (en) 1981-04-17 1981-04-17 Checking circuit for memory beadout output

Country Status (1)

Country Link
JP (1) JPS57172597A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425217B1 (en) * 2002-01-02 2004-03-31 주식회사 하이닉스반도체 Circuit for testing of low VCC detection block

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437445A (en) * 1977-08-29 1979-03-19 Takeda Riken Ind Co Ltd Logic circuit tester
JPS5513430A (en) * 1978-07-11 1980-01-30 Nec Corp Test device for logic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437445A (en) * 1977-08-29 1979-03-19 Takeda Riken Ind Co Ltd Logic circuit tester
JPS5513430A (en) * 1978-07-11 1980-01-30 Nec Corp Test device for logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425217B1 (en) * 2002-01-02 2004-03-31 주식회사 하이닉스반도체 Circuit for testing of low VCC detection block

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