JPS5717086A - Magnifying system of binary pattern - Google Patents

Magnifying system of binary pattern

Info

Publication number
JPS5717086A
JPS5717086A JP9136480A JP9136480A JPS5717086A JP S5717086 A JPS5717086 A JP S5717086A JP 9136480 A JP9136480 A JP 9136480A JP 9136480 A JP9136480 A JP 9136480A JP S5717086 A JPS5717086 A JP S5717086A
Authority
JP
Japan
Prior art keywords
pattern
compensated
line
dot
disturbance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9136480A
Other languages
Japanese (ja)
Other versions
JPS6057264B2 (en
Inventor
Yoshiteru Mifune
Toshiaki Katahira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55091364A priority Critical patent/JPS6057264B2/en
Publication of JPS5717086A publication Critical patent/JPS5717086A/en
Publication of JPS6057264B2 publication Critical patent/JPS6057264B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformation in the plane of the image
    • G06T3/40—Scaling the whole image or part thereof
    • G06T3/4023—Decimation- or insertion-based scaling, e.g. pixel or line decimation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/20—Image preprocessing
    • G06V10/32—Normalisation of the pattern dimensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Image Processing (AREA)
  • Editing Of Facsimile Originals (AREA)

Abstract

PURPOSE:To realize a high-speed magnifying process with an optional ratio of magnification with use of a small-capacity storage device, by compensating the disturbance of an oblique line dot pattern which is caused by the magnifying process through a replacement with a compensated pattern. CONSTITUTION:An original pattern is supplied through a reading part 21 and shifted to an input storage part 23 by an amount equivalent to 1-dot line. For this pattern, a decision is carried out whether or not the standard pattern exists in a square area of 3Xdots near the intersection between an insertion row i and insertion line j through a pattern detecting part 24. If the standard pattern exists, both the position and the type of the pattern and detected and stored. After this detection, the standard pattern is transferred to an output storage part 26 after an insertion through an insertion part 25 for magnification with every dot line. Then an magnified pattern of 4X4 dots to be compensated as a gate part 27 is transferred to a compensating register 31 to be replaced with the compensated patterns of compensated pattern registers 29 and 30 and by an indication given from the part 24. In such way, the disturbance of an oblique line pattern can be compensated during a magnifying process.
JP55091364A 1980-07-03 1980-07-03 Binary pattern expansion method Expired JPS6057264B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55091364A JPS6057264B2 (en) 1980-07-03 1980-07-03 Binary pattern expansion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55091364A JPS6057264B2 (en) 1980-07-03 1980-07-03 Binary pattern expansion method

Publications (2)

Publication Number Publication Date
JPS5717086A true JPS5717086A (en) 1982-01-28
JPS6057264B2 JPS6057264B2 (en) 1985-12-13

Family

ID=14024320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55091364A Expired JPS6057264B2 (en) 1980-07-03 1980-07-03 Binary pattern expansion method

Country Status (1)

Country Link
JP (1) JPS6057264B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181359A (en) * 1982-04-16 1983-10-24 Yokogawa Hokushin Electric Corp Picture data processor
JPS5949078A (en) * 1982-09-13 1984-03-21 Sanyo Electric Co Ltd Rounding processing method of picture display device
JPS60172081A (en) * 1984-02-16 1985-09-05 シャープ株式会社 Expanded pattern generator
JPS6145279A (en) * 1984-08-09 1986-03-05 株式会社東芝 Smoothing circuit
JPS6182277A (en) * 1984-09-29 1986-04-25 Toshiba Corp Smoothing processor
JPS63112723A (en) * 1986-10-28 1988-05-17 Nippon Ester Co Ltd Polyester based binder fiber

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181359A (en) * 1982-04-16 1983-10-24 Yokogawa Hokushin Electric Corp Picture data processor
JPS5949078A (en) * 1982-09-13 1984-03-21 Sanyo Electric Co Ltd Rounding processing method of picture display device
JPH0339434B2 (en) * 1982-09-13 1991-06-13 Sanyo Electric Co
JPS60172081A (en) * 1984-02-16 1985-09-05 シャープ株式会社 Expanded pattern generator
JPS6145279A (en) * 1984-08-09 1986-03-05 株式会社東芝 Smoothing circuit
JPH0251516B2 (en) * 1984-08-09 1990-11-07 Toshiba Kk
JPS6182277A (en) * 1984-09-29 1986-04-25 Toshiba Corp Smoothing processor
JPS63112723A (en) * 1986-10-28 1988-05-17 Nippon Ester Co Ltd Polyester based binder fiber

Also Published As

Publication number Publication date
JPS6057264B2 (en) 1985-12-13

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