JPS5759264A - Vector arithmetic processing method - Google Patents

Vector arithmetic processing method

Info

Publication number
JPS5759264A
JPS5759264A JP13421980A JP13421980A JPS5759264A JP S5759264 A JPS5759264 A JP S5759264A JP 13421980 A JP13421980 A JP 13421980A JP 13421980 A JP13421980 A JP 13421980A JP S5759264 A JPS5759264 A JP S5759264A
Authority
JP
Japan
Prior art keywords
memory
operator
processing capacity
result
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13421980A
Other languages
Japanese (ja)
Other versions
JPS634224B2 (en
Inventor
Satoru Kawai
Masanori Mogi
Hideo Miyanaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13421980A priority Critical patent/JPS5759264A/en
Publication of JPS5759264A publication Critical patent/JPS5759264A/en
Publication of JPS634224B2 publication Critical patent/JPS634224B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Abstract

PURPOSE:To carry out the replacement of a memory address in N times overlap for an operator having a low level of processing capacity as compared with an operator having a high level of processing capacity, and as a result, it is satisfactory to virtually carry out the common and same access process from the side of a memory. CONSTITUTION:A system includes operators 12-A and 12-B having the 1:N processing capacity plus a memory 11 consisting of memory registers 11-R0-11-RP. In such system, the address replace emerging at the N-th time is decided to be effective. Thus the operator 12-B scans by N times repetitively a series of element data belonging to the 1st and 2nd memory registers and at the same time, takes N pieces plus the residual element data into a buffer register 21 at the reading side. The result of arithmetic is temporarily stored in a buffer register 22 at the writing side, and then the result of arithmetic corresponding to N pieces of data are stored in the 3rd memory register consecutively and en bloc. The other residual data are stored after the lapse of a prescribed period of time.
JP13421980A 1980-09-29 1980-09-29 Vector arithmetic processing method Granted JPS5759264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13421980A JPS5759264A (en) 1980-09-29 1980-09-29 Vector arithmetic processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13421980A JPS5759264A (en) 1980-09-29 1980-09-29 Vector arithmetic processing method

Publications (2)

Publication Number Publication Date
JPS5759264A true JPS5759264A (en) 1982-04-09
JPS634224B2 JPS634224B2 (en) 1988-01-28

Family

ID=15123201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13421980A Granted JPS5759264A (en) 1980-09-29 1980-09-29 Vector arithmetic processing method

Country Status (1)

Country Link
JP (1) JPS5759264A (en)

Also Published As

Publication number Publication date
JPS634224B2 (en) 1988-01-28

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