JPS5710871A - Vector operation processing method - Google Patents

Vector operation processing method

Info

Publication number
JPS5710871A
JPS5710871A JP8610980A JP8610980A JPS5710871A JP S5710871 A JPS5710871 A JP S5710871A JP 8610980 A JP8610980 A JP 8610980A JP 8610980 A JP8610980 A JP 8610980A JP S5710871 A JPS5710871 A JP S5710871A
Authority
JP
Japan
Prior art keywords
instruction
processing part
comparing
operation processing
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8610980A
Other languages
Japanese (ja)
Other versions
JPS6116111B2 (en
Inventor
Tetsuo Okamoto
Shigeaki Okuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8610980A priority Critical patent/JPS5710871A/en
Publication of JPS5710871A publication Critical patent/JPS5710871A/en
Publication of JPS6116111B2 publication Critical patent/JPS6116111B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

PURPOSE:To prevent the fact that a following instruction catches up with a preceding instruction, by providing plural processing units on an operation processing means, etc., the like. CONSTITUTION:Plural instruction processing parts are provided on an operation processing part 14, and for instance, one is made an adding instruction processing part 14-1, and the other is made a comparing instruction processing part 14-2. It is constituted so that a comparison processing ends by 6 cycle time, by inserting a dummy cycle in this comparing instruction processing part 14-2. In case when an adding instruction and a comparing instruction are transferred as an instruction V1 and an instruction V2, respectively, the adding instruction is processed by 6 cycle time in the adding instruction processing part 14-1. Subsequently, the transferred comparing instruction is also processed by 6 cycle time since the dummy cycle is inserted, and its write-in stage is not superposed.
JP8610980A 1980-06-25 1980-06-25 Vector operation processing method Granted JPS5710871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8610980A JPS5710871A (en) 1980-06-25 1980-06-25 Vector operation processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8610980A JPS5710871A (en) 1980-06-25 1980-06-25 Vector operation processing method

Publications (2)

Publication Number Publication Date
JPS5710871A true JPS5710871A (en) 1982-01-20
JPS6116111B2 JPS6116111B2 (en) 1986-04-28

Family

ID=13877529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8610980A Granted JPS5710871A (en) 1980-06-25 1980-06-25 Vector operation processing method

Country Status (1)

Country Link
JP (1) JPS5710871A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227829A (en) * 1985-07-30 1987-02-05 Fujitsu Ltd Control system for multiplex load instruction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227829A (en) * 1985-07-30 1987-02-05 Fujitsu Ltd Control system for multiplex load instruction
JPH0578053B2 (en) * 1985-07-30 1993-10-28 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6116111B2 (en) 1986-04-28

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