JPH0339434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rounding processing method for an image display device such as a teletext receiver.

In a text broadcasting system, text information data multiplexed during the vertical retrace period of a television signal is extracted on the receiver side and stored in an image memory.
Already stored data is read out and displayed on a picture tube in synchronization with a television synchronization signal.

Among these teletext systems, especially regarding the Japanese pattern system, one (unit) pixel displayed on the picture tube has a width of approximately 175 nsec. in the horizontal direction and consists of two scanning lines in the vertical direction. has been done. For this reason, if the data read from the image memory is directly displayed, the slanted portions of characters, etc. on the picture tube become difficult to see as shown in FIG. 1a. Therefore, the pixel data corresponding to the above-mentioned slope etc. is 1/1/2 in the front or rear direction of this pixel.
It has been considered to display the image by expanding it by two pixels, and this is generally called rounding processing.

Such rounding processing has already been adopted in the code-based British Teletext system, but the Teletext method cannot be directly applied to the Japanese pattern-based teletext system. First of all, in the pattern method, the displayed pattern is not independent for each character, but may be continuous across several display blocks, so unlike the code method, the pattern displayed is for each character. This is because rounding processing cannot be performed in units of 1 byte that constitutes the data. Also the second
In addition, the pattern method can display much higher definition than the code method, so
This is because it is necessary to ensure that the definition is not impaired due to the rounding process.

In view of this, the present invention proposes a rounding processing method suitable for pattern-based image display, and the details thereof will be explained below.

2 and 3 illustrate the principle of the rounding method of the present invention. That is, in the present invention, when displaying the data of each line read from the image memory by line scanning, the pixel data to be displayed from now on the line currently being displayed (hereinafter abbreviated as display line) is Figure 2 a, b
D ₀ ), the pixel data adjacent to before and after this D ₀
D ₁ , D ₂ and a line displayed immediately before or after the display line (hereinafter referred to as the front line or rear line) at the same horizontal position as each of the data D ₁ , D ₀ , and D ₂ Compare with data D ₃ , D ₄ , D ₅ ,
Depending on the comparison result, the data _D0 is displayed as is, or the first half or the second half of the data is inverted (hereinafter referred to as half dot processing) and displayed. At that time, in the above-mentioned teletext system, as shown in Figure 1 above, the ratio is 2:1.
Interlaced screen display is performed, and the same data is displayed once each in odd-numbered fields and once in even-numbered fields. The respective data D ₀ to _{D 5} on the line are compared.

To explain this point in detail with reference to Figure 3, the figure shows the case of displaying an odd field, and in this case, the data to be displayed on the display line
D ₀ is half-dot processed as shown in figures a to d.
There are four modes. That is, for convenience of explanation, the hatched parts in figures a to d indicate data corresponding to characters and graphic parts (corresponding to binary data "1"), and the unhatched parts indicate data (corresponding to the background). Similarly, the data on the display line as shown in figure a, for example,
D ₀ is background data “0”, data D ₁ on this display line and data D ₄ on the previous line are character and graphic data “1”, and data D ₂ on the display line
When the data _D5 of the previous line is background data "0", the first half of the pixels of the data _D0 is inverted to character/graphic data "1". It is clear from FIG. 1 mentioned above that in this case, the rounding process is realized by inverting the first half of the data _D0 . And b in Figure 3
The same applies to cases of ~d. Also, in the case of an even number field (not shown), as can be seen by considering the previous line of each of a to d in the same figure as the rear line, as in the case of an odd number field, the display line is Data of
Depending on D ₀ and the surrounding data D ₁ to _{D 5} (display line and rear line), it is determined whether to perform half-dot processing on the first half or second half of the data D ₀ . .

FIG. 4 shows an example of a circuit for obtaining data read out from an image memory and performing rounding processing in accordance with the principles of the present invention. In the figure, a latch circuit 1 latches the data of the previous line or the next line, which is read out in parallel byte by byte via a data bus (not shown), and in the case of an odd field, the The data is latched, and in the case of an even field, the data of the next line is latched. Further, the first shift register 2 takes in display line data similarly read out from the image memory, and this is the same for both odd and even fields. At this time, data of 1 byte each of the display line and the previous or next line is read out from the image memory in a time-division manner, and first, the data of the previous line or the next line is read out from the latch circuit 1.
The display line data is then loaded into the first shift register 2. Then, at the timing when the data of the display line is loaded into the first shift register 2, the data of the previous line or the next line latched by the latch circuit 1 is loaded into the second shift register 3. . Therefore, when the first and second shift registers 2 and 3 are serially read out using the display clock, each pixel data located at the same horizontal position on the previous two lines is simultaneously read out from each register. That will happen.

Next, the first inverter 4 and the first 2D flip-flops 5 and 6 convert the data of the previous line or the subsequent line in the second shift register 3 into data D for each one pixel explained in FIGS. 2 and 3. ₃ , _D4 , _D5
This is for simultaneously taking out the second
inverter 7 and third and fourth D flip-flops 8,
9 is the same data for each one pixel D ₁ , D ₀ , from the display line data in the first shift register 1.
This is for taking out ₂ D at the same time. and,
These and the first AND gate 10 determine whether or not to half-dot process the latter half of the pixel data D ₀ on the display line. It is determined whether or not to perform half-dot processing on the first half of the pixels of data _D0 . In this case, the data D ₁ , D ₀ , D ₂ of the display line and the data D ₃ , D ₄ of the front or rear line are used for the former judgment, and the data D ₅ of the front or rear line is not used. As can be seen from Figure 3 above, this judgment requires the above data.
This is because D ₅ is not necessary. Furthermore, the reason why the data _D3 of the previous or subsequent line is not used for the latter determination is also due to the same reason.

Furthermore, the circuit consisting of the third inverter 12, the fifth and sixth D flip-flops 13, 14, and the OR gate 15 outputs the aforementioned judgment outputs, that is, the outputs of the first and second AND gates 10, 11, and the data D ₀ on the display line. The Q output of the 3D flip-flop 8 is obtained, and processing is performed to invert the background data "0" for 1/2 pixel in the first half or the second half of the data D ₀ into character/graphic data "1". The output of this circuit, ie, the output of the OR gate 15, is led to the picture tube and displayed.

The time chart for each part in Figure 4 is an example of the pixel pattern displayed on the screen (the one shown in correspondence with Figure 5a is Figure 5b) (in the figure, odd and even indicate odd and even fields. (The waveforms are shown respectively in the case of
Considering D ₁ , D ₀ , D ₂ and D ₃ , D ₄ , D ₅ , from A and B in the same figure, D ₁ = D ₀ = “0”, D ₂ = “1”, and D ₃
= D ₅ = “0” and D ₄ = “1”, therefore, the output of the second _AND gate 11 (indicated by (odd) becomes "1", and at this time, the output of the first AND gate 10 (odd in Figure C) becomes "0". Since the output of the second AND gate 11 is delayed by one pixel by the fifth D flip-flop 13, the output of the flip-flop 13 becomes "1" during the next period tb to tc. Further, even during this period, the output of the first AND gate 10 remains "0". On the other hand, the Q output of the 6th D flip-flop 14 is 1/
It is delayed by 2 pixels, and is further delayed by 1 pixel from the display line data (FIG. 2B) due to the 3D flip-flop 8, so in the end, as shown in FIG. 1”. Then, the output of the first AND gate 10 (C in the same figure) and the
Since the output of the 5D flip-flop 13 and the output of the sixth flip-flop 14 (FIG. 1) are combined in the OR gate 15, the output of this OR gate 15 (OD in the diagram) is Since this output is delayed by 1 1/2 pixels from the display line data mentioned above (FIG. 2B), as can be seen from the comparison between FIG. The portion corresponding to the first half pixel of _D0 is inverted from "0" to "1" (the hatched portion in the figure). The same holds true for other data and even fields. Therefore, in the operation model of FIG. 5, the reverse hatched portion shown in a of FIG. 5 is subjected to half-dot processing.

As explained above, in the rounding processing method of the present invention, data D ₀ for one pixel to be displayed on the display line is converted into data D ₁ , D ₂ for each pixel adjacent before and after that pixel. as well as,
It is compared with data D ₃ , D ₄ , D ₅ located at the same horizontal position as each of the previous three pixels on the front or rear line, and half-dot processing is performed on the first half or the second half of the data D ₀ according to the comparison result. Therefore, even if the image data of each line read from the image memory represents continuous characters or figures, half dots can be accurately applied only to the necessary parts such as the slopes of the characters or figures. Therefore, it is suitable for image display in pattern-based teletext receivers and the like.

[Brief explanation of the drawing]

Fig. 1 is a display pattern diagram for explaining rounding processing, Figs. 2 and 3 are diagrams for explaining the principle of the rounding processing method of the present invention, and Fig. 4 is an embodiment of the present invention. FIG. 5 is a circuit block diagram showing a time chart of each part thereof, together with a display pattern. 1... Latch circuit, 2, 3... Shift register, 5, 6... D flip-flop.

Claims (1)

[Scope of Claims] 1. An image memory that stores pixel data of each line is provided, and when the data read from the memory is displayed by horizontal line scanning, the pixel data read from the memory or The data D ₀ of the pixel to be displayed on the line that is to be displayed, and the data D ₁ of the pixels adjacent before and after that pixel, respectively.
D ₂ and each data D ₃ , D ₄ , D ₅ of the three pixels on the line that is at the same horizontal position as each of these three pixels D ₀ , D ₁ , D ₂ and displayed immediately before or after the above line. ,
Each data of 6 pixels consisting of D ₀ , D ₁ , D ₂ , D ₃ ,
In a rounding processing method for an image display device, in which a comparison operation is performed on D ₄ and D ₅ , and half-dot processing is performed on the first half or the second half of the pixel to be displayed according to the comparison result, A rounding processing method for an image display device, characterized in that the half-dot processing is allowed only when the values of both data D ₁ and D ₂ of the pixels adjacent to each other before and after a pixel are different.