JPS5717069A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS5717069A JPS5717069A JP9155980A JP9155980A JPS5717069A JP S5717069 A JPS5717069 A JP S5717069A JP 9155980 A JP9155980 A JP 9155980A JP 9155980 A JP9155980 A JP 9155980A JP S5717069 A JPS5717069 A JP S5717069A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- stored
- occupied
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Abstract
PURPOSE:To ensure a smooth process of transfer, by storing the transfer data sucessively to the 1st or 2nd buffer memory while the common bus for the devices excepting those including a floppy disk memory device is occupied and transferring the data when the common bus is not occupied. CONSTITUTION:The transfer data is stored successively 11 in a read mode and while a common bus 6 is occupied when a data transfer request is given. When the occupancy of the bus 6 is cancelled, the affirmative answer signal sent from a direct memory access control circuit 14 is applied to a buffer 11. And the stored data is delivered in an FIFO style. In the case of a write mode, the data transferred from a main memory 2 is stored in the 2nd buffer memory 12 via a memory 2 and a bus 6. Then the data stored in the memory 12 is sent into a floppy disk control circuit 8 in a proper timing. Thus if an idle area of a byte is produced in the memory 12, the data of a byte is successively transferred from the memory 2 according to the idle area of the memory 12.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9155980A JPS5717069A (en) | 1980-07-04 | 1980-07-04 | Data transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9155980A JPS5717069A (en) | 1980-07-04 | 1980-07-04 | Data transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5717069A true JPS5717069A (en) | 1982-01-28 |
Family
ID=14029860
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9155980A Pending JPS5717069A (en) | 1980-07-04 | 1980-07-04 | Data transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5717069A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03285453A (en) * | 1990-03-30 | 1991-12-16 | Sharp Corp | Facsimile equipment |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50117327A (en) * | 1973-02-01 | 1975-09-13 | ||
JPS5247636A (en) * | 1975-10-15 | 1977-04-15 | Toshiba Corp | Control method for transmitting information |
JPS5417639A (en) * | 1977-07-08 | 1979-02-09 | Mitsubishi Electric Corp | Terminal equipment |
-
1980
- 1980-07-04 JP JP9155980A patent/JPS5717069A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50117327A (en) * | 1973-02-01 | 1975-09-13 | ||
JPS5247636A (en) * | 1975-10-15 | 1977-04-15 | Toshiba Corp | Control method for transmitting information |
JPS5417639A (en) * | 1977-07-08 | 1979-02-09 | Mitsubishi Electric Corp | Terminal equipment |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03285453A (en) * | 1990-03-30 | 1991-12-16 | Sharp Corp | Facsimile equipment |
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