JPS57159116A - Initial reception channel set circuit for electronic tuner - Google Patents

Initial reception channel set circuit for electronic tuner

Info

Publication number
JPS57159116A
JPS57159116A JP4320881A JP4320881A JPS57159116A JP S57159116 A JPS57159116 A JP S57159116A JP 4320881 A JP4320881 A JP 4320881A JP 4320881 A JP4320881 A JP 4320881A JP S57159116 A JPS57159116 A JP S57159116A
Authority
JP
Japan
Prior art keywords
voltage
output
high level
tuning
electronic tuner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4320881A
Other languages
Japanese (ja)
Inventor
Susumu Ayaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4320881A priority Critical patent/JPS57159116A/en
Publication of JPS57159116A publication Critical patent/JPS57159116A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/18—Automatic scanning over a band of frequencies

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To achieve the shift to a normal automatic search when voltages are coincident, by changing a tuning voltage while the tuning voltage of an electronic tuner and a voltage from a preset voltage generating means set to generate a prescribed voltage. CONSTITUTION:When an output of an NAND gate 24 is set to high level after the application of a main power supply, a terminal 4 goes to high level via a diode D3 and a terminal 6. Thus, transistors(TR) Q1 and Q2 are conductive and the output of NOR gates 21 and 22 go to low and high level respectively. The base of a TRQ3 goes to high level from a diode D1 via a resistor R9. Thus, a TRQ4 is conductive, a capacitor C1 is charged, and a tuning voltage is gradually increased. When the tuning voltage increases and a minus side voltage is increased than a plus side voltage of an operational amplifier 19, the output of the operational amplifier 19 inverts from high to low potential. Thus, the output of an NAND gate 24 constituting FFs changes from high to low output and this value is stored. The tuning control after this storage is made with normal automatic search systems.
JP4320881A 1981-03-26 1981-03-26 Initial reception channel set circuit for electronic tuner Pending JPS57159116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4320881A JPS57159116A (en) 1981-03-26 1981-03-26 Initial reception channel set circuit for electronic tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4320881A JPS57159116A (en) 1981-03-26 1981-03-26 Initial reception channel set circuit for electronic tuner

Publications (1)

Publication Number Publication Date
JPS57159116A true JPS57159116A (en) 1982-10-01

Family

ID=12657496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4320881A Pending JPS57159116A (en) 1981-03-26 1981-03-26 Initial reception channel set circuit for electronic tuner

Country Status (1)

Country Link
JP (1) JPS57159116A (en)

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