JPS57157347A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS57157347A
JPS57157347A JP4221881A JP4221881A JPS57157347A JP S57157347 A JPS57157347 A JP S57157347A JP 4221881 A JP4221881 A JP 4221881A JP 4221881 A JP4221881 A JP 4221881A JP S57157347 A JPS57157347 A JP S57157347A
Authority
JP
Japan
Prior art keywords
bit
data
serial
multiplexer
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4221881A
Other languages
Japanese (ja)
Inventor
Shinji Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4221881A priority Critical patent/JPS57157347A/en
Publication of JPS57157347A publication Critical patent/JPS57157347A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To reduce the hardware for a multiplexer and a data bus, by converting an output data of each memory plane into a data train of 1-bit, selecting a serial data, performing serial parallel conversion again and transmitting the result to a control section of each device. CONSTITUTION:A parallel data in 32-bit from 0-31 of a memory plane 30 is entried to a shift register 31, shifted left and outputted as a serial output data in 1-bit from 0-bit to 31-bit every time a clock pulse is inputted, and inputted to a multiplexer 33. A serial data selected at it is arranged in time division from 0 bit to the 31-th bit and inputted to a shift register 35. This serial data 34 is replaced with 32 sets of clock pulses from 0-bit to the 31-th bit, serial/parallel conversion is made, a parallel data 36 in 32-bit is again outputted, and this output is transmitted to a device control section. Thus, the circuit constitution of the multiplexer is simplified.
JP4221881A 1981-03-23 1981-03-23 Data transfer system Pending JPS57157347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4221881A JPS57157347A (en) 1981-03-23 1981-03-23 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4221881A JPS57157347A (en) 1981-03-23 1981-03-23 Data transfer system

Publications (1)

Publication Number Publication Date
JPS57157347A true JPS57157347A (en) 1982-09-28

Family

ID=12629896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4221881A Pending JPS57157347A (en) 1981-03-23 1981-03-23 Data transfer system

Country Status (1)

Country Link
JP (1) JPS57157347A (en)

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