JPS57153441A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57153441A
JPS57153441A JP56037890A JP3789081A JPS57153441A JP S57153441 A JPS57153441 A JP S57153441A JP 56037890 A JP56037890 A JP 56037890A JP 3789081 A JP3789081 A JP 3789081A JP S57153441 A JPS57153441 A JP S57153441A
Authority
JP
Japan
Prior art keywords
film
section
wiring
coated
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56037890A
Other languages
Japanese (ja)
Inventor
Shoji Madokoro
Shiro Hagiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP56037890A priority Critical patent/JPS57153441A/en
Publication of JPS57153441A publication Critical patent/JPS57153441A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]

Abstract

PURPOSE:To improve the corrosiveness of a metal for wiring to moisture by previously removing an insulating film containing a high-concentration phosphorus impurity under the bonding pad and circumference of the metal for wiring when the metal for wiring is formed onto the insulating film. CONSTITUTION:A thick field oxide film 2 is shaped to the circumferential section of a P type semiconductor substrate 1, the surface of the substrate 1 surrounded by the film 2 is coated with a thin gate oxide film 3, one part of the film 3 is removed, N type source and drain regions are diffused and formed to the substrate 1 exposed, a polycrystal Si film 4 coating the edge section of the film 2 is shaped onto the film 3, and the whole surface containing these films is coated with the PSG film 6 containing phosphorus at high concentration. The film 6 of a section where a bonding pad section 8 must be formed through a contact photo-lithography is removed selectively through etching, and an electrode extracting hole 7 is also shaped. Accordingly, the pad section 8 is positioned onto the field oxide film 2, and an internal wiring section 9 is formed into the hole 7, and coated with a protective film 10.
JP56037890A 1981-03-18 1981-03-18 Semiconductor device Pending JPS57153441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56037890A JPS57153441A (en) 1981-03-18 1981-03-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56037890A JPS57153441A (en) 1981-03-18 1981-03-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57153441A true JPS57153441A (en) 1982-09-22

Family

ID=12510127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56037890A Pending JPS57153441A (en) 1981-03-18 1981-03-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57153441A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002256B1 (en) * 1999-12-27 2006-02-21 Oki Electric Industry Co., Ltd. Semiconductor device having wiring patterns and dummy patterns covered with insulating layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002256B1 (en) * 1999-12-27 2006-02-21 Oki Electric Industry Co., Ltd. Semiconductor device having wiring patterns and dummy patterns covered with insulating layer

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