JPS57152230A - Logical gate circuit - Google Patents
Logical gate circuitInfo
- Publication number
- JPS57152230A JPS57152230A JP3697581A JP3697581A JPS57152230A JP S57152230 A JPS57152230 A JP S57152230A JP 3697581 A JP3697581 A JP 3697581A JP 3697581 A JP3697581 A JP 3697581A JP S57152230 A JPS57152230 A JP S57152230A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- inverter
- circuit
- trq1
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00307—Modifications for increasing the reliability for protection in bipolar transistor circuits
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Abstract
PURPOSE:To prevent malfunction and to reduce power consumption by providing a diode whose anode and cathode are connected to the emitter of the 1st PNP transistor (TR) of an inverter circuit and to that of the 2nd PNPTR of an NAND circuit. CONSTITUTION:An inverter TRQ1 receives the 1st input signal, and an inverter TRQ4 receives the 2nd input signal. An output signal from the TRQ1 is sent to an emitter follower TRQ2, and while a diode D8 is connected between the output of the TRQ1 and that of the TRQ4, the emitter output terminal of the TRQ2 is grounded through a diode D7. This diode D7 shifts the threshold level of an inverter circuit 10, and the diode D8 inhibits a current flowing through the resistance R1 of the circuit 10 from flowing to a terminal 2 through the diode D5 of an NAND circuit 20 when the input terminals 1 and 2 are at a high and a low potential respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3697581A JPH0249574B2 (en) | 1981-03-13 | 1981-03-13 | RONRIGEETOKAIRO |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3697581A JPH0249574B2 (en) | 1981-03-13 | 1981-03-13 | RONRIGEETOKAIRO |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57152230A true JPS57152230A (en) | 1982-09-20 |
JPH0249574B2 JPH0249574B2 (en) | 1990-10-30 |
Family
ID=12484749
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3697581A Expired - Lifetime JPH0249574B2 (en) | 1981-03-13 | 1981-03-13 | RONRIGEETOKAIRO |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0249574B2 (en) |
-
1981
- 1981-03-13 JP JP3697581A patent/JPH0249574B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0249574B2 (en) | 1990-10-30 |
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