JPS57147194A - Address buffer - Google Patents
Address bufferInfo
- Publication number
- JPS57147194A JPS57147194A JP56031752A JP3175281A JPS57147194A JP S57147194 A JPS57147194 A JP S57147194A JP 56031752 A JP56031752 A JP 56031752A JP 3175281 A JP3175281 A JP 3175281A JP S57147194 A JPS57147194 A JP S57147194A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- gate
- capacity
- flip flop
- switching circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
- H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
Landscapes
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031752A JPS57147194A (en) | 1981-03-05 | 1981-03-05 | Address buffer |
US06/354,498 US4458337A (en) | 1981-03-05 | 1982-03-03 | Buffer circuit |
IE493/82A IE52567B1 (en) | 1981-03-05 | 1982-03-04 | Buffer circuit |
DE8282301133T DE3268738D1 (en) | 1981-03-05 | 1982-03-05 | Buffer circuit |
EP82301133A EP0060105B1 (en) | 1981-03-05 | 1982-03-05 | Buffer circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031752A JPS57147194A (en) | 1981-03-05 | 1981-03-05 | Address buffer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57147194A true JPS57147194A (en) | 1982-09-10 |
JPH0215953B2 JPH0215953B2 (US08197722-20120612-C00042.png) | 1990-04-13 |
Family
ID=12339745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56031752A Granted JPS57147194A (en) | 1981-03-05 | 1981-03-05 | Address buffer |
Country Status (5)
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61110394A (ja) * | 1984-10-31 | 1986-05-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
US4825409A (en) * | 1985-05-13 | 1989-04-25 | Wang Laboratories, Inc. | NMOS data storage cell for clocked shift register applications |
JPS628614A (ja) * | 1985-07-05 | 1987-01-16 | Nec Corp | 入力インバ−タ回路 |
US4952826A (en) * | 1985-07-05 | 1990-08-28 | Nec Corporation | Signal input circuit utilizing flip-flop circuit |
JPS62205597A (ja) * | 1986-03-05 | 1987-09-10 | Toshiba Corp | 半導体感知増幅回路 |
JPH0284811A (ja) * | 1988-01-30 | 1990-03-26 | Nec Corp | 入力インバータ回路 |
US5144168A (en) * | 1990-08-17 | 1992-09-01 | Texas Instruments Incorporated | Self latching input buffer |
US5402387A (en) * | 1992-03-12 | 1995-03-28 | Sharp Kabushiki Kaisha | Semiconductor memory |
JP5620428B2 (ja) * | 2012-03-26 | 2014-11-05 | 株式会社東芝 | 電池セル監視回路、および電池セル監視システム |
US9553584B2 (en) * | 2014-12-23 | 2017-01-24 | International Business Machines Corporation | Level-shifting latch |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5373039A (en) * | 1976-12-13 | 1978-06-29 | Nippon Telegr & Teleph Corp <Ntt> | Sense amplifier |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4038567A (en) * | 1976-03-22 | 1977-07-26 | International Business Machines Corporation | Memory input signal buffer circuit |
US4053873A (en) * | 1976-06-30 | 1977-10-11 | International Business Machines Corporation | Self-isolating cross-coupled sense amplifier latch circuit |
US4224533A (en) * | 1978-08-07 | 1980-09-23 | Signetics Corporation | Edge triggered flip flop with multiple clocked functions |
-
1981
- 1981-03-05 JP JP56031752A patent/JPS57147194A/ja active Granted
-
1982
- 1982-03-03 US US06/354,498 patent/US4458337A/en not_active Expired - Lifetime
- 1982-03-04 IE IE493/82A patent/IE52567B1/en not_active IP Right Cessation
- 1982-03-05 DE DE8282301133T patent/DE3268738D1/de not_active Expired
- 1982-03-05 EP EP82301133A patent/EP0060105B1/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5373039A (en) * | 1976-12-13 | 1978-06-29 | Nippon Telegr & Teleph Corp <Ntt> | Sense amplifier |
Also Published As
Publication number | Publication date |
---|---|
EP0060105A2 (en) | 1982-09-15 |
JPH0215953B2 (US08197722-20120612-C00042.png) | 1990-04-13 |
EP0060105B1 (en) | 1986-01-29 |
EP0060105A3 (en) | 1983-06-15 |
DE3268738D1 (en) | 1986-03-13 |
IE820493L (en) | 1982-09-05 |
IE52567B1 (en) | 1987-12-09 |
US4458337A (en) | 1984-07-03 |
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