JPS57141569A - Method and device for test of integrated circuit - Google Patents

Method and device for test of integrated circuit

Info

Publication number
JPS57141569A
JPS57141569A JP56026495A JP2649581A JPS57141569A JP S57141569 A JPS57141569 A JP S57141569A JP 56026495 A JP56026495 A JP 56026495A JP 2649581 A JP2649581 A JP 2649581A JP S57141569 A JPS57141569 A JP S57141569A
Authority
JP
Japan
Prior art keywords
test
circuit
circuits
parallel
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56026495A
Other languages
Japanese (ja)
Inventor
Eiki Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56026495A priority Critical patent/JPS57141569A/en
Publication of JPS57141569A publication Critical patent/JPS57141569A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Abstract

PURPOSE:To prevent the loss of test processing time, by continuing the test by exchanging one of the IC circuits being in waiting without giving any effect to other, circuits under the test, in accordance with the end of the test or the occurrence of a fault for one of IC circuits to be tested in parallel. CONSTITUTION:IC circuits 4a and 4b undergo the test via measuring circuits 2a and 2b connected in parallel to a control part 1, multiplex circuits 3a and 3b, etc. and according to the test items 7-11 which receive the circulating designation. Then an IC circuit 5a, etc. which is connected to the circuit 3a, etc. and queuing is designated according to the end of all tests of the circuit 4a, etc. or the decision of a fault. Thus the circuit 4a is changed to the circuit 5b without giving any effect to the test of the circuit 4b to continue the parallel test with no interruption. In such way, the time loss for the test process is prevented.
JP56026495A 1981-02-25 1981-02-25 Method and device for test of integrated circuit Pending JPS57141569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56026495A JPS57141569A (en) 1981-02-25 1981-02-25 Method and device for test of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56026495A JPS57141569A (en) 1981-02-25 1981-02-25 Method and device for test of integrated circuit

Publications (1)

Publication Number Publication Date
JPS57141569A true JPS57141569A (en) 1982-09-01

Family

ID=12195067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56026495A Pending JPS57141569A (en) 1981-02-25 1981-02-25 Method and device for test of integrated circuit

Country Status (1)

Country Link
JP (1) JPS57141569A (en)

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