JPS57139857A - Abnormal state relief system of stored program - Google Patents

Abnormal state relief system of stored program

Info

Publication number
JPS57139857A
JPS57139857A JP56024545A JP2454581A JPS57139857A JP S57139857 A JPS57139857 A JP S57139857A JP 56024545 A JP56024545 A JP 56024545A JP 2454581 A JP2454581 A JP 2454581A JP S57139857 A JPS57139857 A JP S57139857A
Authority
JP
Japan
Prior art keywords
abnormal state
memory
period
detecting
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56024545A
Other languages
Japanese (ja)
Inventor
Tatsuo Yokoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AIHON KK
Aiphone Co Ltd
Original Assignee
AIHON KK
Aiphone Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AIHON KK, Aiphone Co Ltd filed Critical AIHON KK
Priority to JP56024545A priority Critical patent/JPS57139857A/en
Publication of JPS57139857A publication Critical patent/JPS57139857A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To decide as an abnormal state when a period for detecting an abnormal state is larger, than the specified reference period, by incorporating a signal having a prescribed period for detecting an abnormal state in a program, detecting its signal, and comparing a specified reference period being longer than the longest time, with said period. CONSTITUTION:A CPU1 is connected to memories 3, 4 through a DATA BUS2. The memory 3 is a read-only IC memory (ROM) and takes charge of a program area. Also, the memory 4 is a writable IC memory (RAM) and takes charge of a data area. In a program stored in the memory, a signal having a prescribed period for detecting an abnormal state is incorporated and is set to the time being equal to the longest processing time t1. A control line CONTROL 9 is connected to the CPU1, the memories 3, 4 and a gate 6, respectively, and an address bus 5 and the control line 9 are connected to a PORT10. An output of the port 10 is applied through a flip-flop OSFF11 to a non-mask interruption terminal MM1 of the CPU1.
JP56024545A 1981-02-20 1981-02-20 Abnormal state relief system of stored program Pending JPS57139857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56024545A JPS57139857A (en) 1981-02-20 1981-02-20 Abnormal state relief system of stored program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56024545A JPS57139857A (en) 1981-02-20 1981-02-20 Abnormal state relief system of stored program

Publications (1)

Publication Number Publication Date
JPS57139857A true JPS57139857A (en) 1982-08-30

Family

ID=12141116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56024545A Pending JPS57139857A (en) 1981-02-20 1981-02-20 Abnormal state relief system of stored program

Country Status (1)

Country Link
JP (1) JPS57139857A (en)

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