JPS57138149A - Mounting method for chip - Google Patents

Mounting method for chip

Info

Publication number
JPS57138149A
JPS57138149A JP56023989A JP2398981A JPS57138149A JP S57138149 A JPS57138149 A JP S57138149A JP 56023989 A JP56023989 A JP 56023989A JP 2398981 A JP2398981 A JP 2398981A JP S57138149 A JPS57138149 A JP S57138149A
Authority
JP
Japan
Prior art keywords
frame
chip
forming frame
adhered
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56023989A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6220693B2 (https=
Inventor
Kozo Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindo Denshi Kogyo KK
Original Assignee
Shindo Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindo Denshi Kogyo KK filed Critical Shindo Denshi Kogyo KK
Priority to JP56023989A priority Critical patent/JPS57138149A/ja
Publication of JPS57138149A publication Critical patent/JPS57138149A/ja
Publication of JPS6220693B2 publication Critical patent/JPS6220693B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP56023989A 1981-02-20 1981-02-20 Mounting method for chip Granted JPS57138149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56023989A JPS57138149A (en) 1981-02-20 1981-02-20 Mounting method for chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56023989A JPS57138149A (en) 1981-02-20 1981-02-20 Mounting method for chip

Publications (2)

Publication Number Publication Date
JPS57138149A true JPS57138149A (en) 1982-08-26
JPS6220693B2 JPS6220693B2 (https=) 1987-05-08

Family

ID=12125982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56023989A Granted JPS57138149A (en) 1981-02-20 1981-02-20 Mounting method for chip

Country Status (1)

Country Link
JP (1) JPS57138149A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0278250A (ja) * 1988-09-14 1990-03-19 Matsushita Electric Works Ltd 半導体パッケージの封止枠の装着方法
CN102469693A (zh) * 2010-11-12 2012-05-23 速码波科技股份有限公司 覆晶封装结构及其可携式通信装置与芯片封胶的工艺方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303587A (ja) * 1989-05-16 1990-12-17 Dainippon Ink & Chem Inc 浄水装置および浄水方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0278250A (ja) * 1988-09-14 1990-03-19 Matsushita Electric Works Ltd 半導体パッケージの封止枠の装着方法
CN102469693A (zh) * 2010-11-12 2012-05-23 速码波科技股份有限公司 覆晶封装结构及其可携式通信装置与芯片封胶的工艺方法

Also Published As

Publication number Publication date
JPS6220693B2 (https=) 1987-05-08

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