JPS57135496A - P-rom compensating circuit - Google Patents

P-rom compensating circuit

Info

Publication number
JPS57135496A
JPS57135496A JP2067281A JP2067281A JPS57135496A JP S57135496 A JPS57135496 A JP S57135496A JP 2067281 A JP2067281 A JP 2067281A JP 2067281 A JP2067281 A JP 2067281A JP S57135496 A JPS57135496 A JP S57135496A
Authority
JP
Japan
Prior art keywords
rom
circuit
roms
pulse
vibrator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2067281A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6134179B2 (enrdf_load_stackoverflow
Inventor
Satoru Suzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2067281A priority Critical patent/JPS57135496A/ja
Publication of JPS57135496A publication Critical patent/JPS57135496A/ja
Publication of JPS6134179B2 publication Critical patent/JPS6134179B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Read Only Memory (AREA)
JP2067281A 1981-02-14 1981-02-14 P-rom compensating circuit Granted JPS57135496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2067281A JPS57135496A (en) 1981-02-14 1981-02-14 P-rom compensating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2067281A JPS57135496A (en) 1981-02-14 1981-02-14 P-rom compensating circuit

Publications (2)

Publication Number Publication Date
JPS57135496A true JPS57135496A (en) 1982-08-21
JPS6134179B2 JPS6134179B2 (enrdf_load_stackoverflow) 1986-08-06

Family

ID=12033684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2067281A Granted JPS57135496A (en) 1981-02-14 1981-02-14 P-rom compensating circuit

Country Status (1)

Country Link
JP (1) JPS57135496A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008225983A (ja) * 2007-03-14 2008-09-25 Fujitsu Ltd パリティエラー復旧回路
JP2012113783A (ja) * 2010-11-25 2012-06-14 Nec Computertechno Ltd 半導体集積回路装置、制御記憶装置の制御方法及びプログラム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008225983A (ja) * 2007-03-14 2008-09-25 Fujitsu Ltd パリティエラー復旧回路
JP2012113783A (ja) * 2010-11-25 2012-06-14 Nec Computertechno Ltd 半導体集積回路装置、制御記憶装置の制御方法及びプログラム

Also Published As

Publication number Publication date
JPS6134179B2 (enrdf_load_stackoverflow) 1986-08-06

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